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Document Number: 337344-003
8th and 9th Generation Intel® Core™
Processor Families
Datasheet, Volume 1 of 2
Supporting 8th Generation Intel® Core™ Processor Families, Intel® Pentium®
Processors, Intel® Celeron® Processors for U/H/S Platforms, known as Coffee
Lake
Supporting 9th Generation Intel® Core™ Processor Families H/S Platforms,
formerly known as Coffee Lake Refresh
April 2019
Revision 003
2 Datasheet, Volume 1 of 2
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Copyright © 2019, Intel Corporation. All rights reserved.
Datasheet, Volume 1 of 2 3
Contents
1 Introduction ............................................................................................................10
1.1 Processor Volatility Statement.............................................................................12
1.2 Supported Technologies .....................................................................................12
1.3 Power Management Support ...............................................................................13
1.3.1 Processor Core Power Management...........................................................13
1.3.2 System Power Management..................................................................... 13
1.3.3 Memory Controller Power Management......................................................14
1.3.4 Processor Graphics Power Management .....................................................14
1.4 Thermal Management Support ............................................................................14
1.5 Package Support ............................................................................................... 15
1.6 Ballout Information............................................................................................15
1.7 Processor Testability .......................................................................................... 15
1.8 Operating System Support ................................................................................. 15
1.9 Terminology ..................................................................................................... 15
1.10 Related Documents............................................................................................ 18
2 Interfaces................................................................................................................19
2.1 System Memory Interface................................................................................... 19
2.1.1 System Memory Technology Supported ..................................................... 19
2.1.2 System Memory Timing Support............................................................... 22
2.1.3 System Memory Organization Modes......................................................... 23
2.1.4 System Memory Frequency...................................................................... 24
2.1.5 Technology Enhancements of Intel® Fast Memory Access (Intel® FMA) ..........25
2.1.6 Data Scrambling .................................................................................... 25
2.1.7 ECC H-Matrix Syndrome Codes................................................................. 25
2.1.8 DDR I/O Interleaving .............................................................................. 26
2.1.9 Data Swapping.......................................................................................27
2.1.10 DRAM Clock Generation...........................................................................27
2.1.11 DRAM Reference Voltage Generation ......................................................... 28
2.1.12 Data Swizzling ....................................................................................... 28
2.2 PCI Express* Graphics Interface (PEG)................................................................. 28
2.2.1 PCI Express* Support .............................................................................28
2.2.2 PCI Express* Architecture .......................................................................30
2.2.3 PCI Express* Configuration Mechanism .....................................................31
2.2.4 PCI Express* Equalization Methodology ..................................................... 31
2.3 Direct Media Interface (DMI)............................................................................... 32
2.3.1 DMI Lane Reversal and Polarity Inversion ..................................................32
2.3.2 DMI Error Flow.......................................................................................33
2.3.3 DMI Link Down ......................................................................................33
2.4 Processor Graphics ............................................................................................34
2.4.1 API Support (Windows*) ......................................................................... 34
2.4.2 Media Support (Intel® QuickSync and Clear Video Technology HD) ...............34
2.4.3 Switchable/Hybrid Graphics .....................................................................37
2.4.4 Gen 9 LP Video Analytics ......................................................................... 38
2.4.5 Gen 9 LP (9th Generation Low Power) Block Diagram ..................................39
2.4.6 GT2/3 Graphic Frequency ........................................................................39
2.5 Display Interfaces .............................................................................................40
2.5.1 DDI Configuration ..................................................................................40
2.5.2 eDP* Bifurcation ....................................................................................40
2.5.3 Display Technologies............................................................................... 43
2.5.4 DisplayPort* .......................................................................................... 45
4 Datasheet, Volume 1 of 2
2.5.5 High-Definition Multimedia Interface (HDMI*)............................................ 46
2.5.6 Digital Video Interface (DVI) ................................................................... 47
2.5.7 embedded DisplayPort* (eDP*) ............................................................... 47
2.5.8 Integrated Audio.................................................................................... 47
2.5.9 Multiple Display Configurations (Dual Channel DDR) ................................... 48
2.5.10 Multiple Display Configurations (Single Channel DDR) ................................. 49
2.5.11 High-bandwidth Digital Content Protection (HDCP) ..................................... 49
2.5.12 Display Link Data Rate Support................................................................ 50
2.5.13 Display Bit Per Pixel (BPP) Support........................................................... 51
2.5.14 Display Resolution per Link Width ............................................................ 51
2.6 Platform Environmental Control Interface (PECI) ................................................... 51
2.6.1 PECI Bus Architecture............................................................................. 51
3 Technologies........................................................................................................... 54
3.1 Intel® Virtualization Technology (Intel® VT) ......................................................... 54
3.1.1 Intel® Virtualization Technology (Intel® VT) for IA-32, Intel® 64 and Intel®
Architecture (Intel® VT-X)....................................................................... 54
3.1.2 Intel® Virtualization Technology (Intel® VT) for Directed I/O (Intel® VT-d).... 56
3.2 Security Technologies........................................................................................ 59
3.2.1 Intel® Trusted Execution Technology (Intel® TXT) ...................................... 59
3.2.2 Intel® Advanced Encryption Standard New Instructions (Intel® AES-NI)........ 60
3.2.3 PCLMULQDQ (Perform Carry-Less Multiplication Quad Word) Instruction........ 60
3.2.4 Intel® Secure Key.................................................................................. 60
3.2.5 Execute Disable Bit ................................................................................ 61
3.2.6 Boot Guard Technology........................................................................... 61
3.2.7 Intel® Supervisor Mode Execution Protection (SMEP) .................................. 61
3.2.8 Intel® Supervisor Mode Access Protection (SMAP) ...................................... 61
3.2.9 Intel® Memory Protection Extensions (Intel® MPX)..................................... 62
3.2.10 Intel® Software Guard Extensions (Intel® SGX) ......................................... 62
3.2.11 Intel® Virtualization Technology (Intel® VT) for Directed I/O (Intel® VT-d).... 63
3.3 Power and Performance Technologies .................................................................. 63
3.3.1 Intel® Hyper-Threading Technology (Intel® HT Technology) ........................ 63
3.3.2 Intel® Turbo Boost Technology 2.0........................................................... 63
3.3.3 Intel® Thermal Velocity Boost (TVB)......................................................... 64
3.3.4 Intel® Advanced Vector Extensions 2 (Intel® AVX2).................................... 64
3.3.5 Intel® 64 Architecture x2APIC ................................................................. 65
3.3.6 Power Aware Interrupt Routing (PAIR)...................................................... 66
3.3.7 Intel® Transactional Synchronization Extensions (Intel® TSX-NI) ................. 66
3.4 Debug Technologies .......................................................................................... 66
3.4.1 Intel® Processor Trace ........................................................................... 66
4 Power Management ................................................................................................ 67
4.1 Advanced Configuration and Power Interface (ACPI) States Supported ..................... 69
4.2 Processor IA Core Power Management ................................................................. 71
4.2.1 OS/HW Controlled P-states...................................................................... 71
4.2.2 Low-Power Idle States............................................................................ 72
4.2.3 Requesting Low-Power Idle States ........................................................... 73
4.2.4 Processor IA Core C-State Rules .............................................................. 73
4.2.5 Package C-States................................................................................... 75
4.2.6 Package C-States and Display Resolutions................................................. 78
4.3 Integrated Memory Controller (IMC) Power Management........................................ 79
4.3.1 Disabling Unused System Memory Outputs................................................ 79
4.3.2 DRAM Power Management and Initialization .............................................. 79
4.3.3 DDR Electrical Power Gating (EPG) ........................................................... 81
4.3.4 Power Training ...................................................................................... 82
4.4 PCI Express* Power Management ....................................................................... 82
Datasheet, Volume 1 of 2 5
4.5 Direct Media Interface (DMI) Power Management................................................... 83
4.6 Processor Graphics Power Management ................................................................83
4.6.1 Memory Power Savings Technologies ........................................................ 83
4.6.2 Display Power Savings Technologies .........................................................83
4.6.3 Processor Graphics Core Power Savings Technologies ..................................85
4.7 System Agent Enhanced Intel® Speedstep® Technology .........................................85
4.8 Voltage Optimization..........................................................................................86
4.9 ROP (Rest Of Platform) PMIC ..............................................................................86
5 Thermal Management ..............................................................................................87
5.1 Processor Thermal Management .......................................................................... 87
5.1.1 Thermal Considerations ...........................................................................87
5.1.2 Intel® Turbo Boost Technology 2.0 Power Monitoring ..................................88
5.1.3 Intel® Turbo Boost Technology 2.0 Power Control ....................................... 88
5.1.4 Configurable TDP (cTDP) and Low-Power Mode...........................................90
5.1.5 Thermal Management Features ................................................................92
5.1.6 Intel® Memory Thermal Management........................................................ 97
5.2 H/U-Processor Line Thermal and Power Specifications ............................................99
5.3 S-Processor Line Thermal and Power Specifications .............................................. 100
5.3.1 Fan Speed Control Scheme with Digital Thermal Sensor (DTS) 2.0 .............. 103
6 Signal Description ................................................................................................. 105
6.1 System Memory Interface................................................................................. 105
6.2 PCI Express* Graphics (PEG) Signals ................................................................. 108
6.3 Direct Media Interface (DMI) Signals .................................................................. 108
6.4 Reset and Miscellaneous Signals........................................................................ 109
6.5 embedded DisplayPort* (eDP*) Signals .............................................................. 110
6.6 Display Interface Signals .................................................................................. 110
6.7 Processor Clocking Signals................................................................................ 111
6.8 Testability Signals ........................................................................................... 111
6.9 Error and Thermal Protection Signals ................................................................. 112
6.10 Power Sequencing Signals ................................................................................ 112
6.11 Processor Power Rails ...................................................................................... 113
6.12 Ground, Reserved and Non-Critical to Function (NCTF) Signals .............................. 114
6.13 Processor Internal Pull-Up/Pull-Down Terminations .............................................. 115
7 Electrical Specifications ......................................................................................... 116
7.1 Processor Power Rails ..................................................................................... 116
7.1.1 Power and Ground Pins ......................................................................... 116
7.1.2 VCC Voltage Identification (VID) ............................................................. 116
7.2 DC Specifications............................................................................................. 117
7.2.1 Processor Power Rails DC Specifications .................................................. 117
7.2.2 Processor Interfaces DC Specifications .................................................... 127
8 Package Mechanical Specifications ........................................................................ 133
8.1 Package Mechanical Attributes .......................................................................... 133
8.2 Package Loading Specifications ......................................................................... 133
8.3 Package Storage Specifications ......................................................................... 134
Figures
1-1 S/H-Processor Line Platforms ................................................................................... 11
1-2 U-Processor Line Platform........................................................................................12
2-1 Intel® Flex Memory Technology Operations ............................................................... 24
2-2 Interleave (IL) and Non-Interleave (NIL) Modes Mapping.............................................27
2-3 PCI Express* Related Register Structures in the Processor ...........................................31
6 Datasheet, Volume 1 of 2
2-4 Example for DMI Lane Reversal Connection ............................................................... 33
2-5 Video Analytics Common Use Cases ......................................................................... 38
2-6 Gen 9 LP Block Diagram ......................................................................................... 39
2-7 Processor Display Architecture (With 3 DDI Ports as an Example)................................. 45
2-8 DisplayPort* Overview............................................................................................ 46
2-9 HDMI* Overview ................................................................................................... 47
2-10 Example for PECI Host-Clients Connection................................................................. 52
2-11 Example for PECI EC Connection............................................................................. 53
3-1 Device to Domain Mapping Structures ...................................................................... 57
4-1 Processor Power States .......................................................................................... 68
4-2 Processor Package and IA Core C-States................................................................... 69
4-3 Idle Power Management Breakdown of the Processor IA Cores ..................................... 72
4-4 Package C-State Entry and Exit ............................................................................... 76
5-1 Package Power Control ........................................................................................... 89
7-1 Input Device Hysteresis .........................................................................................132
Tables
1-1 Processor Lines ..................................................................................................... 10
1-2 Terminology.......................................................................................................... 15
1-3 Related Documents................................................................................................ 18
2-1 Processor DDR Memory Speed Support..................................................................... 19
2-2 Supported DDR4 Non-ECC UDIMM Module Configurations (S-Processor Lines)................ 20
2-3 Supported DDR4 Non-ECC SODIMM Module Configurations (H/U-Processor Lines) .......... 21
2-4 Supported DDR4 ECC SODIMM Module Configurations (S/H-Processor Lines) ................. 21
2-5 Supported DDR4 Memory Down Device Configurations(H/U-Processor Lines) ................. 21
2-7 Supported LPDDR3 x64 DRAMs Configurations(U-Processor Line) ................................. 22
2-6 Supported LPDDR3 x32 DRAMs Configurations(U/H-Processor Line).............................. 22
2-8 DRAM System Memory Timing Support ..................................................................... 22
2-9 DRAM System Memory Timing Support (LPDDR3) ...................................................... 23
2-10 ECC H-Matrix Syndrome Codes ................................................................................ 25
2-11 Interleave (IL) and Non-Interleave (NIL) Modes Pin Mapping ....................................... 26
2-12 PCI Express* Bifurcation and Lane Reversal Mapping.................................................. 29
2-13 PCI Express* Maximum Transfer Rates and Theoretical Bandwidth ............................... 30
2-14 Hardware Accelerated Video Decoding ...................................................................... 35
2-15 Hardware Accelerated Video Encode ......................................................................... 36
2-16 Switchable/Hybrid Graphics Support......................................................................... 37
2-17 GT2/3 Graphics Frequency (S/H/U-Processor Line) ..................................................... 39
2-18 DDI Ports Availability ............................................................................................. 40
2-19 VGA and Embedded DisplayPort* (eDP*) Bifurcation Summary .................................... 41
2-20 VGA and Embedded DisplayPort* (eDP*) Bifurcation Summary .................................... 41
2-21 VGA and Embedded DisplayPort* (eDP*) Bifurcation Summary .................................... 41
2-22 VGA and Embedded DisplayPort* (eDP*) Bifurcation Summary .................................... 41
2-23 Embedded DisplayPort* (eDP*)/DDI Ports Availability................................................. 41
2-24 Embedded DisplayPort* (eDP*)/DDI Ports Availability................................................. 42
2-25 Embedded DisplayPort* (eDP*)/DDI Ports Availability................................................. 42
2-26 Display Technologies Support .................................................................................. 43
2-27 Display Resolutions and Link Bandwidth for Multi-Stream Transport Calculations ............ 43
2-28 Processor Supported Audio Formats Over HDMI* and DisplayPort* ............................... 48
2-29 Maximum Display Resolution .................................................................................. 48
2-30 U-Processor Display Resolution Configuration ........................................................... 49
2-31 H/S -Processor Line Display Resolution Configuration................................................. 49
2-32 HDCP Display supported Implications Table ............................................................... 50
2-33 Display Link Data Rate Support ............................................................................... 50
2-34 Display Resolution and Link Rate Support ................................................................. 50
Datasheet, Volume 1 of 2 7
2-35 Display Bit Per Pixel (BPP) Support ..........................................................................51
2-36 Supported Resolutions for HBR (2.7 Gbps) by Link Width ............................................51
2-37 Supported Resolutions for HBR2 (5.4 Gbps) by Link Width ..........................................51
4-1 System States ....................................................................................................... 69
4-2 Processor IA Core / Package State Support................................................................ 70
4-3 Integrated Memory Controller (IMC) States................................................................ 70
4-4 PCI Express* Link States......................................................................................... 70
4-5 Direct Media Interface (DMI) States.......................................................................... 70
4-6 G, S, and C Interface State Combinations.................................................................. 71
4-7 Deepest Package C-State Available ........................................................................... 78
4-8 Targeted Memory State Conditions ...........................................................................81
4-9 Package C-States with PCIe* Link States Dependencies...............................................82
5-1 Configurable TDP Modes.......................................................................................... 91
5-2 TDP Specifications (H/U-Processor Line) ....................................................................99
5-3 Package Turbo Specifications (H/U-Processor Line) .....................................................99
5-4 Junction Temperature Specifications ....................................................................... 100
5-5 TDP Specifications (S-Processor Line) ..................................................................... 100
5-6 Low Power and TTV Specifications (S-Processor Line)................................................ 101
5-7 Package Turbo Specifications (S-Processor Lines) ..................................................... 102
5-8 TCONTROL Offset Configuration (S-Processor Line - Client)........................................... 103
5-9 Thermal Margin Slope ........................................................................................... 104
6-1 Signal Tables Terminology ..................................................................................... 105
6-2 LPDDR3 Memory Interface..................................................................................... 105
6-3 DDR4 Memory Interface........................................................................................ 106
6-4 System Memory Reference and Compensation Signals............................................... 108
6-5 PCI Express* Interface.......................................................................................... 108
6-6 DMI Interface Signals ........................................................................................... 108
6-7 Reset and Miscellaneous Signals............................................................................. 109
6-8 embedded DisplayPort* Signals.............................................................................. 110
6-9 Display Interface Signals ....................................................................................... 110
6-10 Processor Clocking Signals..................................................................................... 111
6-11 Testability Signals ................................................................................................ 111
6-12 Error and Thermal Protection Signals ...................................................................... 112
6-13 Power Sequencing Signals ..................................................................................... 112
6-14 Processor Power Rails Signals ................................................................................ 113
6-15 Processor Ground Rails Signals............................................................................... 114
6-16 GND, RSVD, and NCTF Signals ............................................................................... 115
6-17 Processor Internal Pull-Up / Pull-Down Terminations ................................................. 115
7-1 Processor Power Rails ........................................................................................... 116
7-2 Processor IA core (Vcc) Active and Idle Mode DC Voltage and Current Specifications ..... 117
7-3 Processor Graphics (VccGT) Supply DC Voltage and Current Specifications.................... 119
7-4 Memory Controller (VDDQ) Supply DC Voltage and Current Specifications .................... 121
7-5 System Agent (VccSA) Supply DC Voltage and Current Specifications .......................... 122
7-6 Processor I/O (VccIO) Supply DC Voltage and Current Specifications............................ 123
7-7 VCCOPC ,VCCEOPIOVoltage Levels ............................................................................ 124
7-8 Processor OPC (VccOPC), Processor EOPIO (VccEOPIO) Supply DC Voltage and Current
Specifications ...................................................................................................... 124
7-9 Processor OPC (VccOPC_1p8) Supply DC Voltage and Current Specifications................... 124
7-10 Vcc Sustain (VccST) Supply DC Voltage and Current Specifications ............................. 125
7-11 Vcc Sustain Gated (VccSTG) Supply DC Voltage and Current Specifications .................. 125
7-12 Processor PLL (VccPLL) Supply DC Voltage and Current Specifications ......................... 126
7-13 Processor PLL_OC (VccPLL_OC) Supply DC Voltage and Current Specifications.............. 126
7-14 LPDDR3 Signal Group DC Specifications................................................................... 127
7-15 DDR4 Signal Group DC Specifications...................................................................... 128
7-16 PCI Express* Graphics (PEG) Group DC Specifications ............................................... 129
8 Datasheet, Volume 1 of 2
7-17 Digital Display Interface Group DC Specifications (DP/HDMI*) ....................................129
7-18 embedded DisplayPort* (eDP*) Group DC Specifications ............................................130
7-19 CMOS Signal Group DC Specifications......................................................................130
7-20 GTL Signal Group and Open Drain Signal Group DC Specifications ...............................130
7-21 PECI DC Electrical Limits........................................................................................131
8-1 Package Mechanical Attributes................................................................................133
8-3 Package Storage Specifications...............................................................................134
8-2 Package Loading Specifications...............................................................................134
Datasheet, Volume 1 of 2 9
Revision History
§ §
Revision Description Release Date
001 Initial Release April 2018
002
• Added S-Processor 2+2 (35W,65W)
• Added S-Processor 8+2 (95W,80W,65W,35W)
• Added 4-Core GT2 95W
• Removed DC_LL from VCCSA for S SKU
• Added U-Processor 2+3e
• Removed S-Processor 83W Xeon
• Updated Operation System Support for S/H/U Processors
October 2018
003 • Added H-Processor 8+2 April 2019
Introduction
10 Datasheet, Volume 1 of 2
1Introduction
The 8th and 9th Gen Intel® Core™ Processor is built on 14-nanometer process
technology.
The U-Processor Line is offered in a 1-Chip Platform that includes the Intel
® 300 Series
Chipset Families Platform Controller Hub (PCH) die on the same package as the
processor die. Refer Figure 1-2.
The U-Processor Line SKUs are offered with On-Package Cache.
The H-Processor and S-Processor Lines are offered in a 2-Chip Platform. Refer
Figure 1-1.
The following table describes the processor lines covered in this document.
Throughout this document, the 8th and 9th Gen Intel
® Core™ Processor families may
be referred to simply as “processor”. Intel® 300 Series Chipset Families Platform
Controller Hub (PCH) may be referred to simply as “PCH”.
Table 1-1. Processor Lines
Processor Line1Package Base TDP Processor
IA Cores
Graphics
Configuration
On-Package
Cache
Platform
Type
U-Processor Line BGA1528 28W 4GT3 128 MB 1-Chip
2
H-Processor Line BGA1440 45W
4
GT2 N/A 2-Chip6
8
S-Processor Line (DT) LGA1151
35W, 65W, 95W 8
GT2
N/A 2-Chip
35W, 65W, 95W 6
35W, 62W, 65W,
91W 4
35W, 54W, 58W 2
35W, 54W, 58W 2 GT1
95W 8
GT095W, 65W 6
91W, 65W 4
Notes:
1. Processor Lines offering may change.
2. In general, 8th and 9th Gen Intel
® Core™ Processor pairs with Intel® 300 Series Chipset Families Platform
Controller Hub. S-Processor Line (DT) SKUs may also pair with Intel
® Z370, H310c, or B365 chipset SKUs.
Datasheet, Volume 1 of 2 11
Introduction
Figure 1-1. S/H-Processor Line Platforms
Introduction
12 Datasheet, Volume 1 of 2
1.1 Processor Volatility Statement
8th and 9th Gen Intel® Core™ Processor families do not retain any end user data when
powered down and/or when the processor is physically removed.
Note: Power down refers to state which all processor power rails are off.
1.2 Supported Technologies
• Intel® Virtualization Technology (Intel® VT)
• Intel® Active Management Technology 11.0 (Intel® AMT 11.0)
• Intel® Trusted Execution Technology (Intel® TXT)
• Intel® Streaming SIMD Extensions 4.2 (Intel® SSE4.2)
• Intel® Hyper-Threading Technology (Intel® HT Technology)
Figure 1-2. U-Processor Line Platform
Datasheet, Volume 1 of 2 13
Introduction
• Intel® 64 Architecture
• Execute Disable Bit
• Intel® Turbo Boost Technology 2.0
• Intel® Advanced Vector Extensions 2 (Intel® AVX2)
• Intel® Advanced Encryption Standard New Instructions (Intel® AES-NI)
• PCLMULQDQ (Perform Carry-Less Multiplication Quad word) Instruction
• Intel® Secure Key
• Intel® Transactional Synchronization Extensions (Intel® TSX-NI)
• PAIR – Power Aware Interrupt Routing
• SMEP – Supervisor Mode Execution Protection
• Intel® Boot Guard
• On-package Cache Memory
• Intel® Software Guard Extensions (Intel® SGX)
• Intel® Memory Protection Extensions (Intel® MPX)
• GMM Scoring Accelerator
• Intel® Processor Trace
• High Definition Content Protection (HDCP) 2.2
Note: The availability of the features may vary between processor SKUs.
Refer to Chapter 3 for more information.
1.3 Power Management Support
1.3.1 Processor Core Power Management
• Full support of ACPI C-states as implemented by the following processor C-states:
— C0, C1, C1E, C3, C6, C7, C8, C9, C10
• Enhanced Intel® SpeedStep® Technology
Notes:
• Package C-State C10 is supported when S-Processor Line is paired with an Intel
300 Series Chipset Family Platform Controller Hub.
• Package C-State C10 is not supported when S-Processor Line is paired with an Intel
200 Series Chipset Family Platform Controller Hub (e.g., Intel Z370 chipset).
Refer to Section 4.2 for more information.
1.3.2 System Power Management
• S0/S0ix, S3, S4, S5
Refer to Chapter 4, “Power Management” for more information.
Introduction
14 Datasheet, Volume 1 of 2
1.3.3 Memory Controller Power Management
• Disabling Unused System Memory Outputs
• DRAM Power Management and Initialization
• Initialization Role of CKE
• Conditional Self-Refresh
• Dynamic Power Down
• DRAM I/O Power Management
• DDR Electrical Power Gating (EPG)
• Power training
Refer to Section 4.3 for more information.
1.3.4 Processor Graphics Power Management
1.3.4.1 Memory Power Savings Technologies
• Intel® Rapid Memory Power Management (Intel® RMPM)
• Intel® Smart 2D Display Technology (Intel® S2DDT)
1.3.4.2 Display Power Savings Technologies
• Intel® (Seamless and Static) Display Refresh Rate Switching (DRRS) with eDP port
• Intel® Automatic Display Brightness
• Smooth Brightness
• Intel® Display Power Saving Technology (Intel® DPST 6)
• Panel Self-Refresh 2 (PSR 2)
• Low Power Single Pipe (LPSP)
1.3.4.3 Graphics Core Power Savings Technologies
• Intel® Graphics Dynamic Frequency
• Intel® Graphics Render Standby Technology (Intel® GRST)
• Dynamic FPS (Intel® DFPS)
Refer to Section 4.6 for more information.
1.4 Thermal Management Support
• Digital Thermal Sensor
• Intel Adaptive Thermal Monitor
• THERMTRIP# and PROCHOT# support
• On-Demand Mode
• Memory Open and Closed Loop Throttling
• Memory Thermal Throttling
Datasheet, Volume 1 of 2 15
Introduction
• External Thermal Sensor (TS-on-DIMM and TS-on-Board)
• Render Thermal Throttling
• Fan speed control with DTS
• Intel Turbo Boost Technology 2.0 Power Control
Refer to Chapter 5, “Thermal Management” for more information.
1.5 Package Support
The processor is available in the following packages:
• A 46 mm x 24 mm BGA package (BGA1528) for U-Processor Line
• A 42 mm x 28 mm BGA package (BGA1440) for H-Processor Line
• A 37.5 mm x 37.5 mm LGA package (LGA1151) for S-Processor Line
1.6 Ballout Information
Refer to the Related Documents section for document information.
1.7 Processor Testability
An XDP on-board connector is warmly recommended to enable full debug capabilities.
For the processor SKUs, a merged XDP connector is highly recommended to enable
lower C-state debug.
Note: When separate XDP connectors will be used at C8–C10 states, the processor will need
to be waked up using the PCH.
The processor includes boundary-scan for board and system level testability.
1.8 Operating System Support
Processor Line Windows* 10
64-bit OS X Linux* OS Chrome* OS
S-processor line
H-processor line
U-processor line
1.9 Terminology
Yes Yes Yes No
Yes Yes Yes No
Yes Yes No No
Table 1-2. Terminology (Sheet 1 of 3)
Term Description
4K Ultra High Definition (UHD)
AES Advanced Encryption Standard
AGC Adaptive Gain Control
BLT Block Level Transfer
Introduction
16 Datasheet, Volume 1 of 2
BPP Bits per pixel
CDR Clock and Data Recovery
CTLE Continuous Time Linear Equalizer
DDI Digital Display Interface for DP or HDMI*/DVI
DDR4/DDR4-RS Fourth-Generation Double Data Rate SDRAM Memory Technology
RS - Reduced Standby Power
DFE decision feedback equalizer
DMA Direct Memory Access
DMI Direct Media Interface
DP DisplayPort*
DTS Digital Thermal Sensor
ECC Error Correction Code - used to fix DDR transactions errors
eDP* embedded DisplayPort*
EU Execution Unit in the Processor Graphics
GSA Graphics in System Agent
HDCP High-bandwidth Digital Content Protection
HDMI* High Definition Multimedia Interface
IMC Integrated Memory Controller
Intel® 64 Technology 64-bit memory extensions to the IA-32 architecture
Intel® DPST Intel® Display Power Saving Technology
Intel® PTT Intel® Platform Trust Technology
Intel® TSX-NI Intel® Transactional Synchronization Extensions
Intel® TXT Intel® Trusted Execution Technology
Intel® VT
Intel Virtualization Technology. Processor Virtualization, when used in conjunction
with Virtual Machine Monitor software, enables multiple, robust independent
software environments inside a single platform.
Intel® VT-d
Intel Virtualization Technology (Intel VT) for Directed I/O. Intel VT-d is a hardware
assist, under system software (Virtual Machine Manager or OS) control, for enabling
I/O device Virtualization. Intel VT-d also brings robust security by providing
protection from errant DMAs by using DMA remapping, a key feature of Intel VT-d.
IOV I/O Virtualization
ISP Image Signal Processor
LFM Low Frequency Mode. corresponding to the Enhanced Intel
® SpeedStep®
Technology’s lowest voltage/frequency pair. It can be read at MSR CEh [47:40].
LLC Last Level Cache
LPDDR3 Low Power Third-generation Double Data Rate SDRAM memory technology
LPM
Low-Power Mode.The LPM Frequency is less than or equal to the LFM Frequency. The
LPM TDP is lower than the LFM TDP as the LPM configuration limits the processor to
single thread operation
LPSP Low-Power Single Pipe
LSF Lowest Supported Frequency.This frequency is the lowest frequency where
manufacturing confirms logical functionality under the set of operating conditions.
MCP Multi Chip Package - includes the processor and the PCH. In some SKUs it might
have additional On-Package Cache.
MFM Minimum Frequency Mode. MFM is the minimum ratio supported by the processor
and can be read from MSR CEh [55:48].
MLC Mid-Level Cache
Table 1-2. Terminology (Sheet 2 of 3)
Term Description
Datasheet, Volume 1 of 2 17
Introduction
NCTF
Non-Critical to Function. NCTF locations are typically redundant ground or non-
critical reserved balls/lands, so the loss of the solder joint continuity at end of life
conditions will not affect the overall product functionality.
OPC On-Package Cache
PCH
Platform Controller Hub. The chipset with centralized platform capabilities including
the main I/O interfaces along with display connectivity, audio features, power
management, manageability, security, and storage features. The PCH may also be
referred as “chipset”.
PECI Platform Environment Control Interface
PEG PCI Express Graphics
PL1, PL2, PL3 Power Limit 1, Power Limit 2, Power Limit 3
Processor The 64-bit multi-core component (package)
Processor Core
The term “processor core” refers to Si die itself, which can contain multiple
execution cores. Each execution core has an instruction cache, data cache, and 256-
KB L2 cache. All execution cores share the LLC.
Processor Graphics Intel Processor Graphics
PSR Panel Self-Refresh
Rank A unit of DRAM corresponding to four to eight devices in parallel, ignoring ECC.
These devices are usually, but not always, mounted on a single side of a SODIMM.
SCI System Control Interrupt. SCI is used in the ACPI protocol.
SDP Scenario Design Power.
SGX Software Guard Extension
SHA Secure Hash Algorithm
SSC Spread Spectrum Clock
Storage Conditions
A non-operational state. The processor may be installed in a platform, in a tray, or
loose. Processors may be sealed in packaging or exposed to free air. Under these
conditions, processor landings should not be connected to any supply voltages, have
any I/Os biased, or receive any clocks. Upon exposure to “free air” (that is, unsealed
packaging or a device removed from packaging material), the processor should be
handled in accordance with moisture sensitivity labeling (MSL) as indicated on the
packaging material.
STR Suspend to RAM
TAC Thermal Averaging Constant
TCC Thermal Control Circuit
TDP Thermal Design Power
TOB Tolerance Budget
TTV TDP Thermal Test Vehicle TDP
VCC Processor core power supply
VCCGT Processor Graphics Power Supply
VCCIO I/O Power Supply
VCCSA System Agent Power Supply
VCCST Vcc Sustain Power Supply
VDDQ DDR Power Supply
VLD Variable Length Decoding
VPID Virtual Processor ID
VSS Processor Ground
Table 1-2. Terminology (Sheet 3 of 3)
Term Description
Produktspecifikationer
| Varumärke: | Intel |
| Kategori: | Processor |
| Modell: | Core i7-9700K |
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