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AVR® Instruction Set Manual

Introduction

This manual gives an overview and explanation of every instruction available for 8-bit AVR

® devices. Each instruction

has its own section containing functional description, it’s opcode, and syntax, the end state of the status register, and

cycle times.

The manual also contains an explanation of the different addressing modes used by AVR devices and an appendix

listing all modern AVR devices and what instruction it has available.

Table of Contents

Introduction.....................................................................................................................................................1

1. Instruction Set Nomenclature..................................................................................................................6

2. CPU Registers Located in the I/O Space................................................................................................8

2.1. RAMPX, RAMPY, and RAMPZ.....................................................................................................8

2.2. RAMPD........................................................................................................................................ 8

2.3. EIND.............................................................................................................................................8

3. The Program and Data Addressing Modes.............................................................................................9

3.1. Register Direct, Single Register Rd..............................................................................................9

3.2. Register Direct - Two Registers, Rd and Rr................................................................................. 9

3.3. I/O Direct.................................................................................................................................... 10

3.4. Data Direct................................................................................................................................. 10

3.5. Data Indirect............................................................................................................................... 11

3.6. Data Indirect with Pre-decrement............................................................................................... 11

3.7. Data Indirect with Post-increment.............................................................................................. 12

3.8. Data Indirect with Displacement.................................................................................................12

3.9. Program Memory Constant Addressing using the LPM, ELPM, and SPM Instructions............. 13

3.10. Program Memory with Post-increment using the LPM Z+ and ELPM Z+ Instruction................. 13

3.11. Store Program Memory Post-increment.....................................................................................14

3.12. Direct Program Addressing, JMP and CALL.............................................................................. 14

3.13. Indirect Program Addressing, IJMP and ICALL..........................................................................15

3.14. Extended Indirect Program Addressing, EIJMP and EICALL.....................................................15

3.15. Relative Program Addressing, RJMP and RCALL..................................................................... 16

4. Conditional Branch Summary............................................................................................................... 17

5. Instruction Set Summary.......................................................................................................................18

6. Instruction Description...........................................................................................................................24

6.1. ADC – Add with Carry................................................................................................................ 24

6.2. ADD – Add without Carry........................................................................................................... 25

6.3. ADIW – Add Immediate to Word................................................................................................ 26

6.4. AND – Logical AND....................................................................................................................27

6.5. ANDI – Logical AND with Immediate..........................................................................................28

6.6. ASR – Arithmetic Shift Right...................................................................................................... 29

6.7. BCLR – Bit Clear in SREG......................................................................................................... 30

6.8. BLD – Bit Load from the T Bit in SREG to a Bit in Register....................................................... 31

6.9. BRBC – Branch if Bit in SREG is Cleared..................................................................................32

6.10. BRBS – Branch if Bit in SREG is Set......................................................................................... 33

6.11. BRCC – Branch if Carry Cleared................................................................................................34

6.12. BRCS – Branch if Carry Set....................................................................................................... 35

6.13. BREAK – Break..........................................................................................................................36

6.14. BREQ – Branch if Equal.............................................................................................................36

6.15. BRGE – Branch if Greater or Equal (Signed).............................................................................37

6.16. BRHC – Branch if Half Carry Flag is Cleared.............................................................................38

AVR® Instruction Set Manual

6.17. BRHS – Branch if Half Carry Flag is Set....................................................................................39

6.18. BRID – Branch if Global Interrupt is Disabled............................................................................ 40

6.19. BRIE – Branch if Global Interrupt is Enabled............................................................................. 41

6.20. BRLO – Branch if Lower (Unsigned).......................................................................................... 42

6.21. BRLT – Branch if Less Than (Signed)........................................................................................43

6.22. BRMI – Branch if Minus..............................................................................................................44

6.23. BRNE – Branch if Not Equal...................................................................................................... 45

6.24. BRPL – Branch if Plus................................................................................................................46

6.25. BRSH – Branch if Same or Higher (Unsigned).......................................................................... 47

6.26. BRTC – Branch if the T Bit is Cleared........................................................................................48

6.27. BRTS – Branch if the T Bit is Set............................................................................................... 49

6.28. BRVC – Branch if Overflow Cleared.......................................................................................... 50

6.29. BRVS – Branch if Overflow Set..................................................................................................51

6.30. BSET – Bit Set in SREG............................................................................................................ 52

6.31. BST – Bit Store from Bit in Register to T Bit in SREG................................................................53

6.32. CALL – Long Call to a Subroutine..............................................................................................54

6.33. CBI – Clear Bit in I/O Register....................................................................................................55

6.34. CBR – Clear Bits in Register...................................................................................................... 56

6.35. CLC – Clear Carry Flag..............................................................................................................57

6.36. CLH – Clear Half Carry Flag...................................................................................................... 57

6.37. CLI – Clear Global Interrupt Enable Bit...................................................................................... 58

6.38. CLN – Clear Negative Flag........................................................................................................ 59

6.39. CLR – Clear Register................................................................................................................. 60

6.40. CLS – Clear Sign Flag................................................................................................................61

6.41. CLT – Clear T Bit........................................................................................................................62

6.42. CLV – Clear Overflow Flag.........................................................................................................62

6.43. CLZ – Clear Zero Flag................................................................................................................63

6.44. COM – One’s Complement........................................................................................................ 64

6.45. CP – Compare............................................................................................................................65

6.46. CPC – Compare with Carry........................................................................................................66

6.47. CPI – Compare with Immediate................................................................................................. 67

6.48. CPSE – Compare Skip if Equal..................................................................................................68

6.49. DEC – Decrement...................................................................................................................... 69

6.50. DES – Data Encryption Standard...............................................................................................71

6.51. EICALL – Extended Indirect Call to Subroutine......................................................................... 72

6.52. EIJMP – Extended Indirect Jump............................................................................................... 73

6.53. ELPM – Extended Load Program Memory.................................................................................73

6.54. EOR – Exclusive OR.................................................................................................................. 75

6.55. FMUL – Fractional Multiply Unsigned........................................................................................ 76

6.56. FMULS – Fractional Multiply Signed.......................................................................................... 77

6.57. FMULSU – Fractional Multiply Signed with Unsigned................................................................79

6.58. ICALL – Indirect Call to Subroutine............................................................................................80

6.59. IJMP – Indirect Jump..................................................................................................................81

6.60. IN - Load an I/O Location to Register.........................................................................................82

6.61. INC – Increment......................................................................................................................... 83

6.62. JMP – Jump............................................................................................................................... 84

6.63. LAC – Load and Clear................................................................................................................85

6.64. LAS – Load and Set................................................................................................................... 86

AVR® Instruction Set Manual

6.65. LAT – Load and Toggle.............................................................................................................. 86

6.66. LD – Load Indirect from Data Space to Register using X...........................................................87

6.67. LD (LDD) – Load Indirect from Data Space to Register using Y................................................ 89

6.68. LD (LDD) – Load Indirect From Data Space to Register using Z............................................... 90

6.69. LDI – Load Immediate................................................................................................................ 92

6.70. LDS – Load Direct from Data Space.......................................................................................... 93

6.71. LDS (AVRrc) – Load Direct from Data Space............................................................................ 94

6.72. LPM – Load Program Memory................................................................................................... 95

6.73. LSL – Logical Shift Left.............................................................................................................. 96

6.74. LSR – Logical Shift Right........................................................................................................... 97

6.75. MOV – Copy Register................................................................................................................ 98

6.76. MOVW – Copy Register Word................................................................................................... 99

6.77. MUL – Multiply Unsigned......................................................................................................... 100

6.78. MULS – Multiply Signed........................................................................................................... 101

6.79. MULSU – Multiply Signed with Unsigned.................................................................................102

6.80. NEG – Two’s Complement....................................................................................................... 103

6.81. NOP – No Operation................................................................................................................ 104

6.82. OR – Logical OR...................................................................................................................... 105

6.83. ORI – Logical OR with Immediate............................................................................................106

6.84. OUT – Store Register to I/O Location...................................................................................... 107

6.85. POP – Pop Register from Stack...............................................................................................108

6.86. PUSH – Push Register on Stack..............................................................................................109

6.87. RCALL – Relative Call to Subroutine....................................................................................... 110

6.88. RET – Return from Subroutine................................................................................................. 111

6.89. RETI – Return from Interrupt.................................................................................................... 112

6.90. RJMP – Relative Jump............................................................................................................. 113

6.91. ROL – Rotate Left trough Carry................................................................................................114

6.92. ROR – Rotate Right through Carry...........................................................................................115

6.93. SBC – Subtract with Carry........................................................................................................116

6.94. SBCI – Subtract Immediate with Carry SBI – Set Bit in I/O Register....................................... 117

6.95. SBI – Set Bit in I/O Register..................................................................................................... 118

6.96. SBIC – Skip if Bit in I/O Register is Cleared............................................................................. 119

6.97. SBIS – Skip if Bit in I/O Register is Set.................................................................................... 120

6.98. SBIW – Subtract Immediate from Word................................................................................... 121

6.99. SBR – Set Bits in Register....................................................................................................... 122

6.100. SBRC – Skip if Bit in Register is Cleared.................................................................................123

6.101. SBRS – Skip if Bit in Register is Set........................................................................................ 124

6.102. SEC – Set Carry Flag...............................................................................................................125

6.103. SEH – Set Half Carry Flag....................................................................................................... 126

6.104. SEI – Set Global Interrupt Enable Bit.......................................................................................127

6.105. SEN – Set Negative Flag......................................................................................................... 128

6.106. SER – Set all Bits in Register...................................................................................................128

6.107. SES – Set Sign Flag................................................................................................................ 129

6.108. SET – Set T Bit........................................................................................................................ 130

6.109. SEV – Set Overflow Flag......................................................................................................... 131

6.110. SEZ – Set Zero Flag.................................................................................................................132

6.111. SLEEP......................................................................................................................................132

6.112. SPM (AVRe) – Store Program Memory....................................................................................133

AVR® Instruction Set Manual

6.113. SPM (AVRxm, AVRxt) – Store Program Memory.....................................................................135

6.114. ST – Store Indirect From Register to Data Space using Index X.............................................136

6.115. ST (STD) – Store Indirect From Register to Data Space using Index Y.................................. 138

6.116. ST (STD) – Store Indirect From Register to Data Space using Index Z...................................140

6.117. STS – Store Direct to Data Space............................................................................................141

6.118. STS (AVRrc) – Store Direct to Data Space.............................................................................. 142

6.119. SUB – Subtract Without Carry..................................................................................................143

6.120. SUBI – Subtract Immediate......................................................................................................144

6.121. SWAP – Swap Nibbles.............................................................................................................145

6.122. TST – Test for Zero or Minus................................................................................................... 146

6.123. WDR – Watchdog Reset.......................................................................................................... 147

6.124. XCH – Exchange......................................................................................................................148

7. Appendix A Device Core Overview..................................................................................................... 149

7.1. Core Descriptions.....................................................................................................................149

7.2. Device Tables...........................................................................................................................150

8. Revision History.................................................................................................................................. 161

8.1. Rev. DS40002198B - 02/2021..................................................................................................161

8.2. Rev. DS40002198A - 05/2020..................................................................................................161

8.3. Rev.0856L - 11/2016................................................................................................................ 161

8.4. Rev.0856K - 04/2016................................................................................................................161

8.5. Rev.0856J - 07/2014................................................................................................................ 161

8.6. Rev.0856I – 07/2010................................................................................................................ 161

8.7. Rev.0856H – 04/2009...............................................................................................................162

8.8. Rev.0856G – 07/2008.............................................................................................................. 162

8.9. Rev.0856F – 05/2008...............................................................................................................162

The Microchip Website...............................................................................................................................163

Product Change Notification Service..........................................................................................................163

Customer Support...................................................................................................................................... 163

Microchip Devices Code Protection Feature..............................................................................................163

Legal Notice............................................................................................................................................... 164

Trademarks................................................................................................................................................ 164

Quality Management System..................................................................................................................... 165

Worldwide Sales and Service.....................................................................................................................166

AVR® Instruction Set Manual

1. Instruction Set Nomenclature

Status Register (SREG)

SREG Status Register

CCarry Flag

ZZero Flag

NNegative Flag

VTwo’s Complement Overflow Flag

SSign Flag

HHalf Carry Flag

TTransfer Bit

IGlobal Interrupt Enable Bit

Registers and Operands

Rd: Destination (and source) register in the Register File

Rr: Source register in the Register File

R: Result after instruction is executed

K: Constant data

k: Constant address

b: Bit position (0..7) in the Register File or I/O Register

s: Bit position (0..7)in the Status Register

X,Y,Z: Indirect Address Register (X=R27:R26, Y=R29:R28, and Z=R31:R30 or X=RAMPX:R27:R26,

Y=RAMPY:R29:R28, and Z=RAMPZ:R31:R30 if the memory is larger than 64 KB)

A: I/O memory address

q: Displacement for direct addressing

UU Unsigned × Unsigned operands

SS Signed × Signed operands

SU Signed × Unsigned operands

Memory Space Identifiers

DS( ) Represents a pointer to address in data space

PS( ) Represents a pointer to address in program space

I/O(A) I/O space address A

I/O(A,b) Bit position b of the byte in I/O space address A

Rd(n) Bit n in register Rd

Operator

×Arithmetic multiplication

AVR® Instruction Set Manual

Instruction Set Nomenclature

Operands are contained in the sources register (Rr) and destination register (Rd). The result is stored in the

destination register (Rd).

3.3 I/O Direct

Figure 3-3. I/O Direct Addressing

OP Rr/Rd A

Operand address A is contained in the instruction word. Rr/Rd specify the destination or source register.

Note: Some AVR microcontrollers have more peripheral units than can be supported within the 64 locations

reserved in the opcode for I/O direct addressing. The extended I/O memory from address 64 and higher can only be

reached by data addressing, not I/O addressing.

3.4 Data Direct

Figure 3-4. Direct Data Addressing

Data Address

OP Rr/Rd

A 16-bit Data Address is contained in the 16 LSBs of a two-word instruction. Rd/Rr specify the destination or source

AVR® Instruction Set Manual

The Program and Data Addressing Modes

3.5 Data Indirect

Figure 3-5. Data Indirect Addressing

X, Y OR Z - POINTER

The operand address is the contents of the X-, Y-, or the Z-pointer. In AVR devices without SRAM, Data Indirect

Addressing is called Register Indirect Addressing.

3.6 Data Indirect with Pre-decrement

Figure 3-6. Data Indirect Addressing with Pre-decrement

X, Y OR Z - POINTER

The X,- Y-, or the Z-pointer is decremented before the operation. The operand address is the decremented contents

of the X-, Y-, or the Z-pointer.

AVR® Instruction Set Manual

The Program and Data Addressing Modes

3.7 Data Indirect with Post-increment

Figure 3-7. Data Indirect Addressing with Post-increment

X, Y OR Z - POINTER

The X-, Y-, or the Z-pointer is incremented after the operation. The operand address is the content of the X-, Y-, or

the Z-pointer before incrementing.

3.8 Data Indirect with Displacement

Figure 3-8. Data Indirect with Displacement

Y OR Z - POINTER

OP Rr/Rd

The operand address is the result of the q displacement contained in the instruction word added to the Y- or

Z-pointer. Rd/Rr specify the destination or source register.

AVR® Instruction Set Manual

The Program and Data Addressing Modes

3.9 Program Memory Constant Addressing using the LPM, ELPM, and SPM

Instructions

Figure 3-9. Program Memory Constant Addressing

LSb

Z - POINTER

Constant byte address is specified by the Z-pointer contents. The 15 MSbs select word address. For LPM, the LSb

selects low byte if cleared (LSb == 0) or high byte if set (LSb == 1). For SPM, the LSb should be cleared. If ELPM is

used, the RAMPZ Register is used to extend the Z-register.

3.10 Program Memory with Post-increment using the LPM Z+ and ELPM Z+ Instruction

Figure 3-10. Program Memory Addressing with Post-increment

LSb

Z - POINTER

Constant byte address is specified by the Z-pointer contents. The 15 MSbs select word address. The LSb selects low

byte if cleared (LSb == 0) or high byte if set (LSb == 1). If ELPM Z+ is used, the RAMPZ Register is used to extend

the Z-register.

AVR® Instruction Set Manual

The Program and Data Addressing Modes

3.11 Store Program Memory Post-increment

Figure 3-11. Store Program Memory

Z - POINTER

The Z-pointer is incremented by 2 after the operation. Constant byte address is specified by the Z-pointer contents

before incrementing. The 15 MSbs select word address and the LSb should be left cleared.

3.12 Direct Program Addressing, JMP and CALL

Figure 3-12. Direct Program Memory Addressing

Program execution continues at the address immediate in the instruction word.

AVR® Instruction Set Manual

The Program and Data Addressing Modes

3.13 Indirect Program Addressing, IJMP and ICALL

Figure 3-13. Indirect Program Memory Addressing

Z - REGISTER

Program execution continues at the address contained by the Z-register (i.e., the PC is loaded with the contents of

the Z-register).

3.14 Extended Indirect Program Addressing, EIJMP and EICALL

Figure 3-14. Extended Indirect Program Memory Addressing

Z - REGISTER

EIND

Program execution continues at the address contained by the Z-register and the EIND-register (i.e., the PC is loaded

with the contents of the EIND and Z-register).

AVR® Instruction Set Manual

The Program and Data Addressing Modes

3.15 Relative Program Addressing, RJMP and RCALL

Figure 3-15. Relative Program Memory Addressing

Program execution continues at the address PC + k + 1. The relative address k is from -2048 to 2047.

AVR® Instruction Set Manual

The Program and Data Addressing Modes

4. Conditional Branch Summary

One Form Complement Form Comment

Mnemonic

Common

Test

Status

Common

Test

Status

BRGE

Rd ≥ Rr

S == 0 BRLT

Rd < Rr

S == 1 Signed

BRSH C == 0 BRLO C == 1 Unsigned

BRNE Rd ≠ Rr Z == 0 BREQ Rd == Rr Z == 1 Unsigned/Signed

BRBC

SREG(s) == 0 BRBS

SREG(s) == 1 -

BRCC C == 0 BRCS C == 1 Simple

BRPL N == 0 BRMI N == 1 Simple

BRVC V == 0 BRVS V == 1 Simple

Note: The Status Register status is a result of the preceding instruction, for further information see instruction

description. If the preceding instruction is CP, CPI, SUB, or SUBI, the branch will occur according to column

‘Common Test’.

AVR® Instruction Set Manual

Conditional Branch Summary

5. Instruction Set Summary

Several updates of the AVR CPU during its lifetime has resulted in different flavors of the instruction set, especially

for the timing of the instructions. Machine code level of compatibility is intact for all CPU versions with very few

exceptions related to the Reduced Core (AVRrc), though not all instructions are included in the instruction set for all

devices. The table below contains the major versions of the AVR 8-bit CPUs. In addition to the different versions,

there are differences depending on the size of the device memory map. Typically these differences are handled by

a C/EC++ compiler, but users that are porting code should be aware that the code execution can vary slightly in the

number of clock cycles.

Table 5-1. Versions of AVR® 8-bit CPU

Name Description

AVR Original instruction set from 1995

AVRe AVR instruction set extended with the Move Word (MOVW) instruction, and the Load Program

Memory (LPM) instruction has been enhanced. Same timing as AVR.

AVRe+ AVRe instruction set extended with the Multiply (xMULxx) instructions, and if applicable with the

extended range instructions EICALL, EIJMP and ELPM. Same timing as AVR and AVRe. Thus,

tables listing number of clock cycles do not distiguish between AVRe and AVRe+, and use AVRe

to represent both.

AVRxm AVRe+ instruction set extended with the Read Modify Write (RMW) and Data Encryption

Standard (DES) instructions. SPM extended to include SPM Z+2. Significantly different timing

compared to AVR, AVRe, AVRe+.

AVRxt A combination of AVRe+ and AVRxm. Available instructions are the same as AVRe+, but the

timing has been improved compared to AVR, AVRe, AVRe+ and AVRxm.

AVRrc AVRrc has only 16 registers in its register file (R31-R16), and the instruction set is reduced. The

timing is significantly different compared to the AVR, AVRe, AVRe+, AVRxm and AVRxt. Refer to

the instruction set summary for further details.

Table 5-2. Arithmetic and Logic Instructions

Mnemonic Operands Description Operation Flags #Clocks

AVRe

#Clocks

AVRxm

#Clocks

AVRxt

#Clocks

AVRrc

ADD Rd, Rr Add without Carry Rd ← Rd + Rr Z,C,N,V,S,H 1 1 1 1

ADC Rd, Rr Add with Carry Rd ← Rd + Rr + C Z,C,N,V,S,H 1 1 1 1

ADIW Rd, K Add Immediate to Word R[d + 1]:Rd ← R[d + 1]:Rd + K Z,C,N,V,S 2 2 2 N/A

SUB Rd, Rr Subtract without Carry Rd ← Rd - Rr Z,C,N,V,S,H 1 1 1 1

SUBI Rd, K Subtract Immediate Rd ← Rd - K Z,C,N,V,S,H 1 1 1 1

SBC Rd, Rr Subtract with Carry Rd ← Rd - Rr - C Z,C,N,V,S,H 1 1 1 1

SBCI Rd, K Subtract Immediate with

Carry

Rd ← Rd - K - C Z,C,N,V,S,H 1 1 1 1

SBIW Rd, K Subtract Immediate from

Word

R[d + 1]:Rd ← R[d + 1]:Rd - K Z,C,N,V,S 2 2 2 N/A

AND Rd, Rr Logical AND Rd ← Rd Rr Z,N,V,S 1 1 1 1∧

ANDI Rd, K Logical AND with

Immediate

Rd ← Rd K Z,N,V,S 1 1 1 1∧

OR Rd, Rr Logical OR Rd ← Rd v Rr Z,N,V,S 1 1 1 1

ORI Rd, K Logical OR with Immediate Rd ← Rd v K Z,N,V,S 1 1 1 1

EOR Rd, Rr Exclusive OR Rd ← Rd Rr Z,N,V,S 1 1 1 1⊕

AVR® Instruction Set Manual

Instruction Set Summary

...........continued

Mnemonic Operands Description Operation Flags #Clocks

AVRe

#Clocks

AVRxm

#Clocks

AVRxt

#Clocks

AVRrc

COM Rd One’s Complement Rd ← 0xFF - Rd Z,C,N,V,S 1 1 1 1

NEG Rd Two’s Complement Rd ← 0x00 - Rd Z,C,N,V,S,H 1 1 1 1

SBR Rd,K Set Bit(s) in Register Rd ← Rd v K Z,N,V,S 1 1 1 1

CBR Rd,K Clear Bit(s) in Register Rd ← Rd (0xFFh - K) Z,N,V,S 1 1 1 1∧

INC Rd Increment Rd ← Rd + 1 Z,N,V,S 1 1 1 1

DEC Rd Decrement Rd ← Rd - 1 Z,N,V,S 1 1 1 1

TST Rd Test for Zero or Minus Rd ← Rd Rd Z,N,V,S 1 1 1 1∧

CLR Rd Clear Register Rd ← Rd Rd Z,N,V,S 1 1 1 1⊕

SER Rd Set Register Rd ← 0xFF None 1 1 1 1

MUL Rd,Rr Multiply Unsigned R1:R0 ← Rd x Rr (UU) Z,C 2 2 2 N/A

MULS Rd,Rr Multiply Signed R1:R0 ← Rd x Rr (SS) Z,C 2 2 2 N/A

MULSU Rd,Rr Multiply Signed with

Unsigned

R1:R0 ← Rd x Rr (SU) Z,C 2 2 2 N/A

FMUL Rd,Rr Fractional Multiply

Unsigned

R1:R0 ← Rd x Rr<<1 (UU) Z,C 2 2 2 N/A

FMULS Rd,Rr Fractional Multiply Signed R1:R0 ← Rd x Rr<<1 (SS) Z,C 2 2 2 N/A

FMULSU Rd,Rr Fractional Multiply Signed

with Unsigned

R1:R0 ← Rd x Rr<<1 (SU) Z,C 2 2 2 N/A

DES K Data Encryption if (H == 0), R15:R0

if (H == 1), R15:R0

←

Encrypt(R15:R0, K)

Decrypt(R15:R0, K)

N/A 1 / 2 N/A N/A

Table 5-3. Change of Flow Instructions

Mnemonic Operands Description Operation Flags #Clocks

AVRe

#Clocks

AVRxm

#Clocks

AVRxt

#Clocks

AVRrc

RJMP k Relative Jump PC ← PC + k + 1 None 2 2 2 2

IJMP Indirect Jump to (Z) PC(15:0)

PC(21:16)

←

None 2 2 2 2

EIJMP Extended Indirect Jump to (Z) PC(15:0)

PC(21:16)

←

EIND

None 2 2 2 N/A

JMP k Jump PC ← k None 3 3 3 N/A

RCALL k Relative Call Subroutine PC ← PC + k + 1 None 3 / 4

(1) 2 / 3 (1) 2 / 3 3

ICALL Indirect Call to (Z) PC(15:0)

PC(21:16)

←

None 3 / 4(1) 2 / 3 (1) 2 / 3 3

EICALL Extended Indirect Call to (Z) PC(15:0)

PC(21:16)

←

EIND

None 4(1) 3(1) 3 N/A

CALL k Call Subroutine PC ← k None 4 / 5

(1) 3/ 4 (1) 3 /4 N/A

RET Subroutine Return PC ← STACK None 4 / 5

(1) 4 / 5 (1) 4 / 5 6

RETI Interrupt Return PC ← STACK I 4 / 5

(1) 4 / 5 (1) 4 / 5 6

CPSE Rd,Rr Compare, skip if Equal if (Rd == Rr) PC ← PC + 2 or 3 None 1 / 2 / 3 1 / 2 / 3 1 / 2 / 3 1 / 2

CP Rd,Rr Compare Rd - Rr Z,C,N,V,S,H 1 1 1 1

CPC Rd,Rr Compare with Carry Rd - Rr - C Z,C,N,V,S,H 1 1 1 1

AVR® Instruction Set Manual

Instruction Set Summary

...........continued

Mnemonic Operands Description Operation Flags #Clocks

AVRe

#Clocks

AVRxm

#Clocks

AVRxt

#Clocks

AVRrc

CPI Rd,K Compare with Immediate Rd - K Z,C,N,V,S,H 1 1 1 1

SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b) == 0) PC ← PC + 2 or 3 None 1 / 2 / 3 1 / 2 / 3 1 / 2 / 3 1 / 2

SBRS Rr, b Skip if Bit in Register Set if (Rr(b) == 1) PC ← PC + 2 or 3 None 1 / 2 / 3 1 / 2 / 3 1 / 2 / 3 1 / 2

SBIC A, b Skip if Bit in I/O Register Cleared if (I/O(A,b) == 0) PC ← PC + 2 or 3 None 1 / 2 / 3 2 / 3 / 4 1 / 2 / 3 1 / 2

SBIS A, b Skip if Bit in I/O Register Set If (I/O(A,b) == 1) PC ← PC + 2 or 3 None 1 / 2 / 3 2 / 3 / 4 1 / 2 / 3 1 / 2

BRBS s, k Branch if Status Flag Set if (SREG(s) == 1) then

← PC + k + 1 None 1 / 2 1 / 2 1 / 2 1 / 2

BRBC s, k Branch if Status Flag Cleared if (SREG(s) == 0) then

← PC + k + 1 None 1 / 2 1 / 2 1 / 2 1 / 2

BREQ k Branch if Equal if (Z == 1) then PC ← PC + k + 1 None 1 / 2 1 / 2 1 / 2 1 / 2

BRNE k Branch if Not Equal if (Z == 0) then PC ← PC + k + 1 None 1 / 2 1 / 2 1 / 2 1 / 2

BRCS k Branch if Carry Set if (C == 1) then PC ← PC + k + 1 None 1 / 2 1 / 2 1 / 2 1 / 2

BRCC k Branch if Carry Cleared if (C == 0) then PC ← PC + k + 1 None 1 / 2 1 / 2 1 / 2 1 / 2

BRSH k Branch if Same or Higher if (C == 0) then PC ← PC + k + 1 None 1 / 2 1 / 2 1 / 2 1 / 2

BRLO k Branch if Lower if (C == 1) then PC ← PC + k + 1 None 1 / 2 1 / 2 1 / 2 1 / 2

BRMI k Branch if Minus if (N == 1) then PC ← PC + k + 1 None 1 / 2 1 / 2 1 / 2 1 / 2

BRPL k Branch if Plus if (N == 0) then PC ← PC + k + 1 None 1 / 2 1 / 2 1 / 2 1 / 2

BRGE k Branch if Greater or Equal,

Signed

if (S == 0) then PC ← PC + k + 1 None 1 / 2 1 / 2 1 / 2 1 /2

BRLT k Branch if Less Than, Signed if (S == 1) then PC ← PC + k + 1 None 1 / 2 1 / 2 1 / 2 1 / 2

BRHS k Branch if Half Carry Flag Set if (H == 1) then PC ← PC + k + 1 None 1 / 2 1 /2 1 / 2 1 / 2

BRHC k Branch if Half Carry Flag Cleared if (H == 0) then PC ← PC + k + 1 None 1 / 2 1 / 2 1 / 2 1 / 2

BRTS k Branch if T Bit Set if (T == 1) then PC ← PC + k + 1 None 1 / 2 1 / 2 1 / 2 1 / 2

BRTC k Branch if T Bit Cleared if (T == 0) then PC ← PC + k + 1 None 1 / 2 1 / 2 1 / 2 1 / 2

BRVS k Branch if Overflow Flag is Set if (V == 1) then PC ← PC + k + 1 None 1 / 2 1 / 2 1 / 2 1 / 2

BRVC k Branch if Overflow Flag is

Cleared

if (V == 0) then PC ← PC + k + 1 None 1 / 2 1 / 2 1 / 2 1 / 2

BRIE k Branch if Interrupt Enabled if (I == 1) then PC ← PC + k + 1 None 1 / 2 1 / 2 1 / 2 1 / 2

BRID k Branch if Interrupt Disabled if (I == 0) then PC ← PC + k + 1 None 1 / 2 1 / 2 1 / 2 1 / 2

Table 5-4. Data Transfer Instructions

Mnemonic Operands Description Operation Flags #Clocks

AVRe

#Clocks

AVRxm

#Clocks

AVRxt

#Clocks

AVRrc

MOV Rd, Rr Copy Register Rd ← Rr None 1 1 1 1

MOVW Rd, Rr Copy Register Pair R[d + 1]:Rd ← R[r + 1]:Rr None 1 1 1 N/A

LDI Rd, K Load Immediate Rd ← K None 1 1 1 1

LDS Rd, k Load Direct from Data Space Rd ← DS(k) None 2

(1) 3(1)(3) 3(2) 2

LD Rd, X Load Indirect Rd ← DS(X) None 2

(1) 2(1)(3) 2(2) 1 / 2

LD Rd, X+ Load Indirect and Post-Increment Rd

←

DS(X)

X + 1

None 2(1) 2(1)(3) 2(2) 2 / 3

LD Rd, -X Load Indirect and Pre-Decrement X

←

X - 1

DS(X)

None 2(1) 3(1)(3) 2(2) 2 / 3

AVR® Instruction Set Manual

Instruction Set Summary

...........continued

Mnemonic Operands Description Operation Flags #Clocks

AVRe

#Clocks

AVRxm

#Clocks

AVRxt

#Clocks

AVRrc

LD Rd, Y Load Indirect Rd ← DS(Y) None 2

(1) 2(1)(3) 2(2) 1 / 2

LD Rd, Y+ Load Indirect and Post-Increment Rd

←

DS(Y)

Y + 1

None 2(1) 2(1)(3) 2(2) 2 / 3

LD Rd, -Y Load Indirect and Pre-Decrement Y

←

Y - 1

DS(Y)

None 2(1) 3(1)(3) 2(2) 2 / 3

LDD Rd, Y+q Load Indirect with Displacement Rd ← DS(Y + q) None 2

(1) 3(1)(3) 2(2) N/A

LD Rd, Z Load Indirect Rd ← DS(Z) None 2

(1) 2(1)(3) 2(2) 1 / 2

LD Rd, Z+ Load Indirect and Post-Increment Rd

←

DS(Z)

Z+1

None 2(1) 2(1)(3) 2(2) 2 / 3

LD Rd, -Z Load Indirect and Pre-Decrement Z

←

Z - 1

DS(Z)

None 2(1) 3(1)(3) 2(2) 2 / 3

LDD Rd, Z+q Load Indirect with Displacement Rd ← DS(Z + q) None 2

(1) 3(1)(3) 2(2) N/A

STS k, Rr Store Direct to Data Space DS(k) ← Rd None 2

(1) 2(1) 2(2) 1

ST X, Rr Store Indirect DS(X) ← Rr None 2

(1) 1(1) 1(2) 1

ST X+, Rr Store Indirect and Post-Increment DS(X)

←

X + 1

None 2(1) 1(1) 1(2) 1

ST -X, Rr Store Indirect and Pre-Decrement X

DS(X)

←

X - 1

None 2(1) 2(1) 1(2) 2

ST Y, Rr Store Indirect DS(Y) ← Rr None 2

(1) 1(1) 1(2) 1

ST Y+, Rr Store Indirect and Post-Increment DS(Y)

←

Y + 1

None 2(1) 1(1) 1(2) 1

ST -Y, Rr Store Indirect and Pre-Decrement Y

DS(Y)

←

Y - 1

None 2(1) 2(1) 1(2) 2

STD Y+q, Rr Store Indirect with Displacement DS(Y + q) ← Rr None 2

(1) 2(1) 1(2) N/A

ST Z, Rr Store Indirect DS(Z) ← Rr None 2

(1) 1(1) 1(2) 1

ST Z+, Rr Store Indirect and Post-Increment DS(Z)

←

Z + 1

None 2(1) 1(1) 1(2) 1

ST -Z, Rr Store Indirect and Pre-Decrement Z

DS(Z)

←

Z - 1

None 2(1) 2(1) 1(2) 2

STD Z+q,Rr Store Indirect with Displacement DS(Z + q) ← Rr None 2

(1) 2(1) 1(2) N/A

LPM Load Program Memory R0 ← PS(Z) None 3 3 3 N/A

LPM Rd, Z Load Program Memory Rd ← PS(Z) None 3 3 3 N/A

LPM Rd, Z+ Load Program Memory and Post-

Increment

←

PS(Z)

Z + 1

None 3 3 3 N/A

ELPM Extended Load Program Memory R0 ← PS(RAMPZ:Z) None 3 3 3 N/A

ELPM Rd, Z Extended Load Program Memory Rd ← PS(RAMPZ:Z) None 3 3 3 N/A

ELPM Rd, Z+ Extended Load Program Memory

and Post-Increment

(RAMPZ:Z)

←

PS(RAMPZ:Z)

(RAMPZ:Z) + 1

None 3 3 3 N/A

SPM Store Program Memory PS(RAMPZ:Z) ← R1:R0 None -(4) -(4) -(4) N/A

SPM Z+ Store Program Memory and Post-

Increment by 2

PS(RAMPZ:Z)

←

R1:R0

Z + 2

None N/A - (4) -(4) N/A

AVR® Instruction Set Manual

Instruction Set Summary

...........continued

Mnemonic Operands Description Operation Flags #Clocks

AVRe

#Clocks

AVRxm

#Clocks

AVRxt

#Clocks

AVRrc

IN Rd, A In From I/O Location Rd ← I/O(A) None 1 1 1 1

OUT A, Rr Out To I/O Location I/O(A) ← Rr None 1 1 1 1

PUSH Rr Push Register on Stack STACK ← Rr None 2 1

(1) 1 1

POP Rd Pop Register from Stack Rd ← STACK None 2 2

(1) 2 3

XCH Z, Rd Exchange DS(Z) ↔ Rd None N/A 2 N/A N/A

LAS Z, Rd Load and Set DS(Z)

←

Rd v DS(Z)

DS(Z)

None N/A 2 N/A N/A

LAC Z, Rd Load and Clear DS(Z)

←

(0xFF – Rd) DS(Z)∧

DS(Z)

None N/A 2 N/A N/A

LAT Z, Rd Load and Toggle DS(Z)

←

Rd DS(Z)⊕

DS(Z)

None N/A 2 N/A N/A

Table 5-5. Bit and Bit-Test Instructions

Mnemonic Operands Description Operation Flags #Clocks

AVRe

#Clocks

AVRxm

#Clocks

AVRxt

#Clocks

AVRrc

LSL Rd Logical Shift Left C

Rd(n+1)

Rd(0)

←

Rd(7)

Rd(n), n=6...0

Z,C,N,V,H 1 1 1 1

LSR Rd Logical Shift Right C

Rd(n)

Rd(7)

←

Rd(0)

Rd(n+1), n=0...6

Z,C,N,V 1 1 1 1

ROL Rd Rotate Left Through Carry temp

Rd(n+1)

Rd(0)

←

Rd(7)

Rd(n), n=6...0

temp

Z,C,N,V,H 1 1 1 1

ROR Rd Rotate Right Through Carry temp

Rd(n)

Rd(7)

←

Rd(0)

Rd(n+1), n=0...6

temp

Z,C,N,V 1 1 1 1

ASR Rd Arithmetic Shift Right C

Rd(n)

Rd(7)

←

Rd(0)

Rd(n+1), n=0..6

Rd(7)

Z,C,N,V 1 1 1 1

SWAP Rd Swap Nibbles Rd(3..0) ↔ Rd(7..4) None 1 1 1 1

SBI A, b Set Bit in I/O Register I/O(A, b) ← 1 None 2 1 1 1

CBI A, b Clear Bit in I/O Register I/O(A, b) ← 0 None 2 1 1 1

BST Rr, b Bit Store from Register to T T ← Rr(b) T 1 1 1 1

BLD Rd, b Bit load from T to Register Rd(b) ← T None 1 1 1 1

BSET s Flag Set SREG(s) ← 1 SREG(s) 1 1 1 1

BCLR s Flag Clear SREG(s) ← 0 SREG(s) 1 1 1 1

SEC Set Carry C ← 1 C 1 1 1 1

CLC Clear Carry C ← 0 C 1 1 1 1

SEN Set Negative Flag N ← 1 N 1 1 1 1

AVR® Instruction Set Manual

Instruction Set Summary

...........continued

Mnemonic Operands Description Operation Flags #Clocks

AVRe

#Clocks

AVRxm

#Clocks

AVRxt

#Clocks

AVRrc

CLN Clear Negative Flag N ← 0 N 1 1 1 1

SEZ Set Zero Flag Z ← 1 Z 1 1 1 1

CLZ Clear Zero Flag Z ← 0 Z 1 1 1 1

SEI Global Interrupt Enable I ← 1 I 1 1 1 1

CLI Global Interrupt Disable I ← 0 I 1 1 1 1

SES Set Sign Bit S ← 1 S 1 1 1 1

CLS Clear Sign Bit S ← 0 S 1 1 1 1

SEV Set Two’s Complement Overflow V ← 1 V 1 1 1 1

CLV Clear Two’s Complement

Overflow

V ← 0 V 1 1 1 1

SET Set T in SREG T ← 1 T 1 1 1 1

CLT Clear T in SREG T ← 0 T 1 1 1 1

SEH Set Half Carry Flag in SREG H ← 1 H 1 1 1 1

CLH Clear Half Carry Flag in SREG H ← 0 H 1 1 1 1

Table 5-6. MCU Control Instructions

Mnemonic Operands Description Operation Flags #Clocks

AVRe

#Clocks

AVRxm

#Clocks

AVRxt

#Clocks

AVRrc

BREAK Break See the debug interface description None 1 1 1 1

NOP No Operation None 1 1 1 1

SLEEP Sleep See the power management and sleep description None 1 1 1 1

WDR Watchdog Reset See the Watchdog Controller description None 1 1 1 1

Notes:

1. Cycle times for data memory access assume internal RAM access and are not valid for accessing external

RAM.

2. Cycle time for data memory access assumes internal RAM access, and are not valid for access to NVM.

A minimum of one extra cycle must be added when accessing NVM. The additional time varies dependent

on the NVM module implementation. See the NVMCTRL section in the specific devices data sheet for more

information.

3. If the LD instruction is accessing I/O Registers, one cycle can be deducted.

4. Varies with the programming time of the device.

AVR® Instruction Set Manual

Instruction Set Summary

6. Instruction Description

6.1 ADC – Add with Carry

6.1.1 Description

Adds two registers and the contents of the C flag and places the result in the destination register Rd.

Operation:

(i) Rd ← Rd + Rr + C

Syntax: Operands: Program Counter:

(i) ADC Rd,Rr 0 ≤ d ≤ 31, 0 ≤ r ≤ 31 PC ← PC + 1

16-bit Opcode:

0001 11rd dddd rrrr

6.1.2 Status Register (SREG) and Boolean Formula

I T H S V N Z C

– – ⇔⇔⇔⇔⇔⇔

H Rd3 Rr3 Rr3 R3 R3 Rd3∧ ∨ ∧ ∨ ∧

Set if there was a carry from bit 3; cleared otherwise.

S N V, for signed tests.⊕

V Rd7 Rr7 R7 Rd7 Rr7 R7∧ ∧ ∨ ∧ ∧

Set if two’s complement overflow resulted from the operation; cleared otherwise.

N R7

Set if MSB of the result is set; cleared otherwise.

Z R7 R6 R5 R4 R3 R2 R1 R0∧∧∧∧∧∧∧

Set if the result is ; cleared otherwise.0x00

C Rd7 Rr7 Rr7 R7 R7 Rd7∧ ∨ ∧ ∨ ∧

Set if there was a carry from the MSB of the result; cleared otherwise.

R (Result) equals Rd after the operation.

Example:

; Add R1:R0 to R3:R2

add r2,r0 ; Add low byte

adc r3,r1 ; Add with carry high byte

Words 1 (2 bytes)

AVR® Instruction Set Manual

Instruction Description

Table 6-1. Cycles

Name Cycles

AVRe 1

AVRxm 1

AVRxt 1

AVRrc 1

6.2 ADD – Add without Carry

6.2.1 Description

Adds two registers without the C flag and places the result in the destination register Rd.

Operation:

(i) (i) Rd ← Rd + Rr

Syntax: Operands: Program Counter:

(i) ADD Rd,Rr 0 ≤ d ≤ 31, 0 ≤ r ≤ 31 PC ← PC + 1

16-bit Opcode:

0000 11rd dddd rrrr

6.2.2 Status Register (SREG) and Boolean Formula

I T H S V N Z C

– – ⇔⇔⇔⇔⇔⇔

H Rd3 Rr3 Rr3 R3 R3 Rd3∧ ∨ ∧ ∨ ∧

Set if there was a carry from bit 3; cleared otherwise.

S N V, for signed tests.⊕

V Rd7 Rr7 R7 Rd7 Rr7 R7∧ ∧ ∨ ∧ ∧

Set if two’s complement overflow resulted from the operation; cleared otherwise.

N R7

Set if MSB of the result is set; cleared otherwise.

Z R7 R6 R5 R4 R3 R2 R1 R0∧∧∧∧∧∧∧

Set if the result is ; cleared otherwise.0x00

C Rd7 Rr7 Rr7 R7 R7 Rd7∧ ∨ ∧ ∨ ∧

Set if there was a carry from the MSB of the result; cleared otherwise.

R (Result) equals Rd after the operation.

AVR® Instruction Set Manual

Instruction Description

Example:

add r1,r2 ; Add r2 to r1 (r1=r1+r2)

add r28,r28 ; Add r28 to itself (r28=r28+r28)

Words 1 (2 bytes)

Table 6-2. Cycles

Name Cycles

AVRe 1

AVRxm 1

AVRxt 1

AVRrc 1

6.3 ADIW – Add Immediate to Word

6.3.1 Description

Adds an immediate value (0-63) to a register pair and places the result in the register pair. This instruction operates

on the upper four register pairs and is well suited for operations on the Pointer Registers.

This instruction is not available on all devices. Refer to .Appendix A

Operation:

(i) R[d+1]:Rd ← R[d+1]:Rd + K

Syntax: Operands: Program Counter:

(i) ADIW Rd,K d {24,26,28,30}, 0 ≤ K ≤ 63 PC ← PC + 1∈

16-bit Opcode:

1001 0110 KKdd KKKK

6.3.2 Status Register (SREG) and Boolean Formula

I T H S V N Z C

–––⇔⇔⇔⇔⇔

S N V, for signed tests.⊕

V Rdh7 R15∧

Set if two’s complement overflow resulted from the operation; cleared otherwise.

N R15

Set if MSB of the result is set; cleared otherwise.

Z R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0∧ ∧ ∧ ∧ ∧ ∧ ∧ ∧ ∧ ∧ ∧ ∧ ∧ ∧ ∧

Set if the result is ; cleared otherwise.0x0000

C R15 Rdh7∧

AVR® Instruction Set Manual

Instruction Description

Set if there was a carry from the MSB of the result; cleared otherwise.

R (Result) equals R[d+1]:Rd after the operation.

Example:

adiw r24,1 ; Add 1 to r25:r24

adiw ZL,63 ; Add 63 to the Z-pointer(r31:r30)

Words 1 (2 bytes)

Table 6-3. Cycles

Name Cycles

AVRe 2

AVRxm 2

AVRxt 2

AVRrc N/A

6.4 AND – Logical AND

6.4.1 Description

Performs the logical AND between the contents of register Rd and register Rr, and places the result in the destination

Operation:

(i) Rd ← Rd Rr∧

Syntax: Operands: Program Counter:

(i) AND Rd,Rr 0 ≤ d ≤ 31, 0 ≤ r ≤ 31 PC ← PC + 1

16-bit Opcode:

0010 00rd dddd rrrr

6.4.2 Status Register (SREG) and Boolean Formula

I T H S V N Z C

– – – 0 –⇔ ⇔ ⇔

S N V, for signed tests.⊕

V 0

Cleared.

N R7

Set if MSB of the result is set; cleared otherwise.

Z R7 R6 R5 R4 R3 R2 R1 R0∧∧∧∧∧∧∧

Set if the result is ; cleared otherwise.0x00

AVR® Instruction Set Manual

Instruction Description

R (Result) equals Rd after the operation.

Example:

and r2,r3 ; Bitwise and r2 and r3, result in r2

ldi r16,1 ; Set bitmask 0000 0001 in r16

and r2,r16 ; Isolate bit 0 in r2

Words 1 (2 bytes)

Table 6-4. Cycles

Name Cycles

AVRe 1

AVRxm 1

AVRxt 1

AVRrc 1

6.5 ANDI – Logical AND with Immediate

6.5.1 Description

Performs the logical AND between the contents of register Rd and a constant, and places the result in the destination

Operation:

(i) Rd ← Rd K∧

Syntax: Operands: Program Counter:

(i) ANDI Rd,K 16 ≤ d ≤ 31, 0 ≤ K ≤ 255 PC ← PC + 1

16-bit Opcode:

0111 KKKK dddd KKKK

6.5.2 Status Register (SREG) and Boolean Formula

I T H S V N Z C

– – – 0 –⇔ ⇔ ⇔

S N V, for signed tests.⊕

V 0

Cleared.

N R7

Set if MSB of the result is set; cleared otherwise.

Z R7 R6 R5 R4 R3 R2 R1 R0∧∧∧∧∧∧∧

Set if the result is ; cleared otherwise.0x00

R (Result) equals Rd after the operation.

AVR® Instruction Set Manual

Instruction Description

Example:

andi r17,0x0F ; Clear upper nibble of r17

andi r18,0x10 ; Isolate bit 4 in r18

andi r19,0xAA ; Clear odd bits of r19

Words 1 (2 bytes)

Table 6-5. Cycles

Name Cycles

AVRe 1

AVRxm 1

AVRxt 1

AVRrc 1

6.6 ASR – Arithmetic Shift Right

6.6.1 Description

Shifts all bits in Rd one place to the right. Bit 7 is held constant. Bit 0 is loaded into the C flag of the SREG. This

operation effectively divides a signed value by two without changing its sign. The Carry flag can be used to round the

result.

Operation:

(i)

Syntax: Operands: Program Counter:

(i) ASR Rd 0 ≤ d ≤ 31 PC ← PC + 1

16-bit Opcode:

1001 010d dddd 0101

6.6.2 Status Register (SREG) and Boolean Formula

I T H S V N Z C

–––⇔⇔⇔⇔⇔

S N V, for signed tests.⊕

V N C, for N and C after the shift.⊕

N R7. Set if MSB of the result is set; cleared otherwise.

Z R7 R6 R5 R4 R3 R2 R1 R0∧∧∧∧∧∧∧

Set if the result is ; cleared otherwise.0x00

C Rd0

Set if, before the shift, the LSB of Rd was set; cleared otherwise.

AVR® Instruction Set Manual

Instruction Description

R (Result) equals Rd after the operation.

Example:

ldi r16,0x10 ; Load decimal 16 into r16

asr r16 ; r16=r16 / 2

ldi r17,0xFC ; Load -4 in r17

asr r17 ; r17=r17/2

Words 1 (2 bytes)

Table 6-6. Cycles

Name Cycles

AVRe 1

AVRxm 1

AVRxt 1

AVRrc 1

6.7 BCLR – Bit Clear in SREG

6.7.1 Description

Clears a single flag in SREG.

Operation:

(i) SREG(s) ← 0

Syntax: Operands: Program Counter:

(i) BCLR s 0 ≤ s ≤ 7 PC ← PC + 1

16-bit Opcode:

1001 0100 1sss 1000

6.7.2 Status Register (SREG) and Boolean Formula

I T H S V N Z C

⇔⇔⇔⇔⇔⇔⇔⇔

I If (s == 7) then I ← 0, else unchanged.

T If (s == 6) then T ← 0, else unchanged.

H If (s == 5) then H ← 0, else unchanged.

S If (s == 4) then S ← 0, else unchanged.

V If (s == 3) then V ← 0, else unchanged.

N If (s == 2) then N ← 0, else unchanged.

Z If (s == 1) then Z ← 0, else unchanged.

C If (s == 0) then C ← 0, else unchanged.

AVR® Instruction Set Manual

Instruction Description

Example:

bclr 0 ; Clear Carry flag

bclr 7 ; Disable interrupts

Words 1 (2 bytes)

Table 6-7. Cycles

Name Cycles

AVRe 1

AVRxm 1

AVRxt 1

AVRrc 1

6.8 BLD – Bit Load from the T Bit in SREG to a Bit in Register

6.8.1 Description

Copies the T bit in the SREG (Status Register) to bit b in register Rd.

Operation:

(i) Rd(b) ← T

Syntax: Operands: Program Counter:

(i) BLD Rd,b 0 ≤ d ≤ 31, 0 ≤ b ≤ 7 PC ← PC + 1

16 bit Opcode:

1111 100d dddd 0bbb

6.8.2 Status Register (SREG) and Boolean Formula

I T H S V N Z C

– – – – – – – –

Example:

; Copy bit

bst r1,2 ; Store bit 2 of r1 in T bit

bld r0,4 ; Load T bit into bit 4 of r0

Words 1 (2 bytes)

Table 6-8. Cycles

Name Cycles

AVRe 1

AVRxm 1

AVRxt 1

AVR® Instruction Set Manual

Instruction Description

...........continued

Name Cycles

AVRrc 1

6.9 BRBC – Branch if Bit in SREG is Cleared

6.9.1 Description

Conditional relative branch. Tests a single bit in SREG and branches relatively to the PC if the bit is cleared. This

instruction branches relatively to the PC in either direction (PC - 63 ≤ destination ≤ PC + 64). Parameter k is the offset

from the PC and is represented in two’s complement form.

Operation:

(i) If SREG(s) == 0 then PC ← PC + k + 1, else PC ← PC + 1

Syntax: Operands: Program Counter:

(i) BRBC s,k 0 ≤ s ≤ 7, -64 ≤ k ≤ +63 PC ← PC + k + 1

PC ← PC + 1, if the condition is

false

16-bit Opcode:

1111 01kk kkkk ksss

6.9.2 Status Register (SREG) and Boolean Formula

I T H S V N Z C

– – – – – – – –

Example:

cpi r20,5 ; Compare r20 to the value 5

brbc 1,noteq ; Branch if Zero flag cleared

...

noteq: nop ; Branch destination (do nothing)

Words 1 (2 bytes)

Table 6-9. Cycles

Name Cycles

i ii

AVRe 1 2

AVRxm 1 2

AVRxt 1 2

AVRrc 1 2

i) If the condition is false.

ii) If the condition is true.

AVR® Instruction Set Manual

Instruction Description

6.10 BRBS – Branch if Bit in SREG is Set

6.10.1 Description

Conditional relative branch. Tests a single bit in SREG and branches relatively to the PC if the bit is set. This

instruction branches relatively to the PC in either direction (PC - 63 ≤ destination ≤ PC + 64). Parameter k is the offset

from the PC and is represented in two’s complement form.

Operation:

(i) If SREG(s) == 1 then PC ← PC + k + 1, else PC ← PC + 1

Syntax: Operands: Program Counter:

(i) BRBS s,k 0 ≤ s ≤ 7, -64 ≤ k ≤ +63 PC ← PC + k + 1

PC ← PC + 1, if the condition is

false

16-bit Opcode:

1111 00kk kkkk ksss

6.10.2 Status Register (SREG) and Boolean Formula

I T H S V N Z C

– – – – – – – –

Example:

bst r0,3 ; Load T bit with bit 3 of r0

brbs 6,bitset ; Branch T bit was set

...

bitset: nop ; Branch destination (do nothing)

Words 1 (2 bytes)

Table 6-10. Cycles

Name Cycles

i ii

AVRe 1 2

AVRxm 1 2

AVRxt 1 2

AVRrc 1 2

i) If the condition is false.

ii) If the condition is true.

AVR® Instruction Set Manual

Instruction Description

6.11 BRCC – Branch if Carry Cleared

6.11.1 Description

Conditional relative branch. Tests the Carry (C) flag and branches relatively to the PC if C is cleared. This instruction

branches relatively to the PC in either direction (PC - 63 ≤ destination ≤ PC + 64). Parameter k is the offset from the

PC and is represented in two’s complement form. (Equivalent to instruction BRBC 0,k.)

Operation:

(i) If C == 0 then PC ← PC + k + 1, else PC ← PC + 1

Syntax: Operands: Program Counter:

(i) BRCC k -64 ≤ k ≤ +63 PC ← PC + k + 1

PC ← PC + 1, if the condition is

false

16-bit Opcode:

1111 01kk kkkk k000

6.11.2 Status Register (SREG) and Boolean Formula

I T H S V N Z C

– – – – – – – –

Example:

add r22,r23 ; Add r23 to r22

brcc nocarry ; Branch if carry cleared

...

nocarry: nop ; Branch destination (do nothing)

Words 1 (2 bytes)

Table 6-11. Cycles

Name Cycles

i ii

AVRe 1 2

AVRxm 1 2

AVRxt 1 2

AVRrc 1 2

i) If the condition is false.

ii) If the condition is true.

AVR® Instruction Set Manual

Instruction Description

6.12 BRCS – Branch if Carry Set

6.12.1 Description

Conditional relative branch. Tests the Carry (C) flag and branches relatively to the PC if C is set. This instruction

branches relatively to the PC in either direction (PC - 63 ≤ destination ≤ PC + 64). Parameter k is the offset from the

PC and is represented in two’s complement form. (Equivalent to instruction BRBS 0,k.)

Operation:

(i) If C == 1 then PC ← PC + k + 1, else PC ← PC + 1

Syntax: Operands: Program Counter:

(i) BRCS k -64 ≤ k ≤ +63 PC ← PC + k + 1

PC ← PC + 1, if the condition is

false

16-bit Opcode:

1111 00kk kkkk k000

6.12.2 Status Register (SREG) and Boolean Formula

I T H S V N Z C

– – – – – – – –

Example:

cpi r26,0x56 ; Compare r26 with 0x56

brcs carry ; Branch if carry set

...

carry: nop ; Branch destination (do nothing)

Words 1 (2 bytes)

Table 6-12. Cycles

Name Cycles

i ii

AVRe 1 2

AVRxm 1 2

AVRxt 1 2

AVRrc 1 2

i) If the condition is false.

ii) If the condition is true.

AVR® Instruction Set Manual

Instruction Description

6.13 BREAK – Break

6.13.1 Description

The BREAK instruction is used by the On-chip Debug system and not used by the application software. When the

BREAK instruction is executed, the AVR CPU is set in the Stopped state. This gives the On-chip Debugger access to

internal resources.

If the device is locked, or the on-chip debug system is not enabled, the CPU will treat the BREAK instruction as a

NOP and will not enter the Stopped state.

This instruction is not available on all devices. Refer to .Appendix A

Operation:

(i) On-chip Debug system breakpoint instruction.

Syntax: Operands: Program Counter:

(i) BREAK None PC ← PC + 1

16-bit Opcode:

1001 0101 1001 1000

6.13.2 Status Register (SREG) and Boolean Formula

I T H S V N Z C

– – – – – – – –

Words 1 (2 bytes)

Table 6-13. Cycles

Name Cycles

AVRe 1

AVRxm 1

AVRxt 1

AVRrc 1

6.14 BREQ – Branch if Equal

6.14.1 Description

Conditional relative branch. Tests the Zero (Z) flag and branches relatively to the PC if Z is set. If the instruction is

executed immediately after any of the instructions CP, CPI, SUB, or SUBI, the branch will occur only if the unsigned

or signed binary number represented in Rd was equal to the unsigned or signed binary number represented in Rr.

This instruction branches relatively to the PC in either direction (PC - 63 ≤ destination ≤ PC + 64). Parameter k is the

offset from the PC and is represented in two’s complement form. (Equivalent to instruction BRBS 1,k.)

Operation:

(i) If Rd == Rr (Z == 1) then PC ← PC + k + 1, else PC ← PC + 1

Syntax: Operands: Program Counter:

AVR® Instruction Set Manual

Instruction Description

(i) BREQ k -64 ≤ k ≤ +63 PC ← PC + k + 1

PC ← PC + 1, if the condition is

false

16-bit Opcode:

1111 00kk kkkk k001

6.14.2 Status Register (SREG) and Boolean Formula

I T H S V N Z C

– – – – – – – –

Example:

cp r1,r0 ; Compare registers r1 and r0

breq equal ; Branch if registers equal

...

equal: nop ; Branch destination (do nothing)

Words 1 (2 bytes)

Table 6-14. Cycles

Name Cycles

i ii

AVRe 1 2

AVRxm 1 2

AVRxt 1 2

AVRrc 1 2

i) If the condition is false.

ii) If the condition is true.

6.15 BRGE – Branch if Greater or Equal (Signed)

6.15.1 Description

Conditional relative branch. Tests the Sign (S) flag and branches relatively to the PC if S is cleared. If the instruction

is executed immediately after any of the instructions CP, CPI, SUB, or SUBI, the branch will occur only if the signed

binary number represented in Rd was greater than or equal to the signed binary number represented in Rr. This

instruction branches relatively to the PC in either direction (PC - 63 ≤ destination ≤ PC + 64). Parameter k is the offset

from the PC and is represented in two’s complement form. (Equivalent to instruction BRBC 4,k.)

Operation:

(i) If Rd ≥ Rr (S == 0) then PC ← PC + k + 1, else PC ← PC + 1

Syntax: Operands: Program Counter:

AVR® Instruction Set Manual

Instruction Description

(i) BRGE k -64 ≤ k ≤ +63 PC ← PC + k + 1

PC ← PC + 1, if the condition is

false

16-bit Opcode:

1111 01kk kkkk k100

6.15.2 Status Register (SREG) and Boolean Formula

I T H S V N Z C

– – – – – – – –

Example:

cp r11,r12 ; Compare registers r11 and r12

brge greateq ; Branch if r11 ≥ r12 (signed)

...

greateq: nop ; Branch destination (do nothing)

Words 1 (2 bytes)

Table 6-15. Cycles

Name Cycles

i ii

AVRe 1 2

AVRxm 1 2

AVRxt 1 2

AVRrc 1 2

i) If the condition is false.

ii) If the condition is true.

6.16 BRHC – Branch if Half Carry Flag is Cleared

6.16.1 Description

Conditional relative branch. Tests the Half Carry (H) flag and branches relatively to the PC if H is cleared. This

instruction branches relatively to the PC in either direction (PC - 63 ≤ destination ≤ PC + 64). Parameter k is the offset

from the PC and is represented in two’s complement form. (Equivalent to instruction BRBC 5,k.)

Operation:

(i) If H == 0 then PC ← PC + k + 1, else PC ← PC + 1

Syntax: Operands: Program Counter:

(i) BRHC k -64 ≤ k ≤ +63 PC ← PC + k + 1

PC ← PC + 1, if the condition is

false

AVR® Instruction Set Manual

Instruction Description

16-bit Opcode:

1111 01kk kkkk k101

6.16.2 Status Register (SREG) and Boolean Formula

I T H S V N Z C

– – – – – – – –

Example:

brhc hclear ; Branch if Half Carry flag cleared

...

hclear: nop ; Branch destination (do nothing)

Words 1 (2 bytes)

Table 6-16. Cycles

Name Cycles

i ii

AVRe 1 2

AVRxm 1 2

AVRxt 1 2

AVRrc 1 2

i) If the condition is false.

ii) If the condition is true.

6.17 BRHS – Branch if Half Carry Flag is Set

6.17.1 Description

Conditional relative branch. Tests the Half Carry (H) flag and branches relatively to the PC if H is set. This instruction

branches relatively to the PC in either direction (PC - 63 ≤ destination ≤ PC + 64). Parameter k is the offset from the

PC and is represented in two’s complement form. (Equivalent to instruction BRBS 5,k.)

Operation:

(i) If H == 1 then PC ← PC + k + 1, else PC ← PC + 1

Syntax: Operands: Program Counter:

(i) BRHS k -64 ≤ k ≤ +63 PC ← PC + k + 1

PC ← PC + 1, if the condition is

false

16-bit Opcode:

1111 00kk kkkk k101

AVR® Instruction Set Manual

Instruction Description

6.17.2 Status Register (SREG) and Boolean Formula

I T H S V N Z C

– – – – – – – –

Example:

brhs hset ; Branch if Half Carry flag set

...

hset: nop ; Branch destination (do nothing)

Words 1 (2 bytes)

Table 6-17. Cycles

Name Cycles

i ii

AVRe 1 2

AVRxm 1 2

AVRxt 1 2

AVRrc 1 2

i) If the condition is false.

ii) If the condition is true.

6.18 BRID – Branch if Global Interrupt is Disabled

6.18.1 Description

Conditional relative branch. Tests the Global Interrupt Enable (I) bit and branches relatively to the PC if I is cleared.

This instruction branches relatively to the PC in either direction (PC - 63 ≤ destination ≤ PC + 64). Parameter k is the

offset from the PC and is represented in two’s complement form. (Equivalent to instruction BRBC 7,k.)

Operation:

(i) If I == 0 then PC ← PC + k + 1, else PC ← PC + 1

Syntax: Operands: Program Counter:

(i) BRID k -64 ≤ k ≤ +63 PC ← PC + k + 1

PC ← PC + 1, if the condition is

false

16-bit Opcode:

1111 01kk kkkk k111

6.18.2 Status Register (SREG) and Boolean Formula

I T H S V N Z C

– – – – – – – –

AVR® Instruction Set Manual

Instruction Description

Example:

brid intdis ; Branch if interrupt disabled

...

intdis: nop ; Branch destination (do nothing)

Words 1 (2 bytes)

Table 6-18. Cycles

Name Cycles

i ii

AVRe 1 2

AVRxm 1 2

AVRxt 1 2

AVRrc 1 2

i) If the condition is false.

ii) If the condition is true.

6.19 BRIE – Branch if Global Interrupt is Enabled

6.19.1 Description

Conditional relative branch. Tests the Global Interrupt Enable (I) bit and branches relatively to the PC if I is set. This

instruction branches relatively to the PC in either direction (PC - 63 ≤ destination ≤ PC + 64). Parameter k is the offset

from the PC and is represented in two’s complement form. (Equivalent to instruction BRBS 7,k.)

Operation:

(i) If I == 1 then PC ← PC + k + 1, else PC ← PC + 1

Syntax: Operands: Program Counter:

(i) BRIE k -64 ≤ k ≤ +63 PC ← PC + k + 1

PC ← PC + 1, if the condition is

false

16-bit Opcode:

1111 00kk kkkk k111

6.19.2 Status Register (SREG) and Boolean Formula

I T H S V N Z C

– – – – – – – –

Example:

brie inten ; Branch if interrupt enabled

...

inten: nop ; Branch destination (do nothing)

AVR® Instruction Set Manual

Instruction Description

Words 1 (2 bytes)

Table 6-19. Cycles

Name Cycles

i ii

AVRe 1 2

AVRxm 1 2

AVRxt 1 2

AVRrc 1 2

i) If the condition is false.

ii) If the condition is true.

6.20 BRLO – Branch if Lower (Unsigned)

6.20.1 Description

Conditional relative branch. Tests the Carry (C) flag and branches relatively to the PC if C is set. If the instruction is

executed immediately after any of the instructions CP, CPI, SUB, or SUBI, the branch will occur only if the unsigned

binary number represented in Rd was smaller than the unsigned binary number represented in Rr. This instruction

branches relatively to the PC in either direction (PC - 63 ≤ destination ≤ PC + 64). Parameter k is the offset from the

PC and is represented in two’s complement form. (Equivalent to instruction BRBS 0,k.)

Operation:

(i) If Rd < Rr (C == 1) then PC ← PC + k + 1, else PC ← PC + 1

Syntax: Operands: Program Counter:

(i) BRLO k -64 ≤ k ≤ +63 PC ← PC + k + 1

PC ← PC + 1, if the condition is

false

16-bit Opcode:

1111 00kk kkkk k000

6.20.2 Status Register (SREG) and Boolean Formula

I T H S V N Z C

– – – – – – – –

Example:

eor r19,r19 ; Clear r19

loop: inc r19 ; Increase r19

...

cpi r19,0x10 ; Compare r19 with 0x10

brlo loop ; Branch if r19 < 0x10 (unsigned)

nop ; Exit from loop (do nothing)

Words 1 (2 bytes)

AVR® Instruction Set Manual

Instruction Description

Table 6-20. Cycles

Name Cycles

i ii

AVRe 1 2

AVRxm 1 2

AVRxt 1 2

AVRrc 1 2

i) If the condition is false.

ii) If the condition is true.

6.21 BRLT – Branch if Less Than (Signed)

6.21.1 Description

Conditional relative branch. Tests the Sign (S) flag and branches relatively to the PC if S is set. If the instruction

is executed immediately after any of the instructions CP, CPI, SUB, or SUBI, the branch will occur only if the

signed binary number represented in Rd was less than the signed binary number represented in Rr. This instruction

branches relatively to the PC in either direction (PC - 63 ≤ destination ≤ PC + 64). Parameter k is the offset from the

PC and is represented in two’s complement form. (Equivalent to instruction BRBS 4,k.)

Operation:

(i) If Rd < Rr (S == 1) then PC ← PC + k + 1, else PC ← PC + 1

Syntax: Operands: Program Counter:

(i) BRLT k -64 ≤ k ≤ +63 PC ← PC + k + 1

PC ← PC + 1, if the condition is

false

16-bit Opcode:

1111 00kk kkkk k100

6.21.2 Status Register (SREG) and Boolean Formula

I T H S V N Z C

– – – – – – – –

Example:

cp r16,r1 ; Compare r16 to r1

brlt less ; Branch if r16 < r1 (signed)

...

less: nop ; Branch destination (do nothing)

Words 1 (2 bytes)

AVR® Instruction Set Manual

Instruction Description

Table 6-21. Cycles

Name Cycles

i ii

AVRe 1 2

AVRxm 1 2

AVRxt 1 2

AVRrc 1 2

i) If the condition is false.

ii) If the condition is true.

6.22 BRMI – Branch if Minus

6.22.1 Description

Conditional relative branch. Tests the Negative (N) flag and branches relatively to the PC if N is set. This instruction

branches relatively to the PC in either direction (PC - 63 ≤ destination ≤ PC + 64). Parameter k is the offset from the

PC and is represented in two’s complement form. (Equivalent to instruction BRBS 2,k.)

Operation:

(i) If N == 1 then PC ← PC + k + 1, else PC ← PC + 1

Syntax: Operands: Program Counter:

(i) BRMI k -64 ≤ k ≤ +63 PC ← PC + k + 1

PC ← PC + 1, if the condition is

false

16-bit Opcode:

1111 00kk kkkk k010

6.22.2 Status Register (SREG) and Boolean Formula

I T H S V N Z C

– – – – – – – –

Example:

subi r18,4 ; Subtract 4 from r18

brmi negative ; Branch if result negative

...

negative: nop ; Branch destination (do nothing)

Words 1 (2 bytes)

AVR® Instruction Set Manual

Instruction Description

Table 6-22. Cycles

Name Cycles

i ii

AVRe 1 2

AVRxm 1 2

AVRxt 1 2

AVRrc 1 2

i) If the condition is false.

ii) If the condition is true.

6.23 BRNE – Branch if Not Equal

6.23.1 Description

Conditional relative branch. Tests the Zero (Z) flag and branches relatively to the PC if Z is cleared. If the instruction

is executed immediately after any of the instructions CP, CPI, SUB, or SUBI, the branch will occur only if the

unsigned or signed binary number represented in Rd was not equal to the unsigned or signed binary number

represented in Rr. This instruction branches relatively to the PC in either direction (PC - 63 ≤ destination ≤ PC + 64).

Parameter k is the offset from the PC and is represented in two’s complement form. (Equivalent to instruction BRBC

1,k.)

Operation:

(i) If Rd ≠ Rr (Z == 0) then PC ← PC + k + 1, else PC ← PC + 1

Syntax: Operands: Program Counter:

(i) BRNE k -64 ≤ k ≤ +63 PC ← PC + k + 1

PC ← PC + 1, if the condition is

false

16-bit Opcode:

1111 01kk kkkk k001

6.23.2 Status Register (SREG) and Boolean Formula

I T H S V N Z C

– – – – – – – –

Example:

eor r27,r27 ; Clear r27

loop: inc r27 ; Increase r27

...

cpi r27,5 ; Compare r27 to 5

brne loop ; Branch if r27<>5

nop ; Loop exit (do nothing)

Words 1 (2 bytes)

AVR® Instruction Set Manual

Instruction Description

Table 6-23. Cycles

Name Cycles

i ii

AVRe 1 2

AVRxm 1 2

AVRxt 1 2

AVRrc 1 2

i) If the condition is false.

ii) If the condition is true.

6.24 BRPL – Branch if Plus

6.24.1 Description

Conditional relative branch. Tests the Negative (N) flag and branches relatively to the PC if N is cleared. This

instruction branches relatively to the PC in either direction (PC - 63 ≤ destination ≤ PC + 64). Parameter k is the offset

from the PC and is represented in two’s complement form. (Equivalent to instruction BRBC 2,k.)

Operation:

(i) If N == 0 then PC ← PC + k + 1, else PC ← PC + 1

Syntax: Operands: Program Counter:

(i) BRPL k -64 ≤ k ≤ +63 PC ← PC + k + 1

PC ← PC + 1, if the condition is

false

16-bit Opcode:

1111 01kk kkkk k010

6.24.2 Status Register (SREG) and Boolean Formula

I T H S V N Z C

– – – – – – – –

Example:

subi r26,0x50 ; Subtract 0x50 from r26

brpl positive ; Branch if r26 positive

...

positive: nop ; Branch destination (do nothing)

Words 1 (2 bytes)

AVR® Instruction Set Manual

Instruction Description

Table 6-24. Cycles

Name Cycles

i ii

AVRe 1 2

AVRxm 1 2

AVRxt 1 2

AVRrc 1 2

i) If the condition is false.

ii) If the condition is true.

6.25 BRSH – Branch if Same or Higher (Unsigned)

6.25.1 Description

Conditional relative branch. Tests the Carry (C) flag and branches relatively to the PC if C is cleared. If the instruction

is executed immediately after execution of any of the instructions CP, CPI, SUB, or SUBI, the branch will occur only if

the unsigned binary number represented in Rd was greater than or equal to the unsigned binary number represented

in Rr. This instruction branches relatively to the PC in either direction (PC - 63 ≤ destination ≤ PC + 64). Parameter k

is the offset from the PC and is represented in two’s complement form. (Equivalent to instruction BRBC 0,k.)

Operation:

(i) If Rd ≥Rr (C == 0) then PC ← PC + k + 1, else PC ← PC + 1

Syntax: Operands: Program Counter:

(i) BRSH k -64 ≤ k ≤ +63 PC ← PC + k + 1

PC ← PC + 1, if the condition is

false

16-bit Opcode:

1111 01kk kkkk k000

6.25.2 Status Register (SREG) and Boolean Formula

I T H S V N Z C

– – – – – – – –

Example:

subi r19,4 ; Subtract 4 from r19

brsh highsm ; Branch if r19 >= 4 (unsigned)

...

highsm: nop ; Branch destination (do nothing)

Words 1 (2 bytes)

AVR® Instruction Set Manual

Instruction Description

Table 6-25. Cycles

Name Cycles

i ii

AVRe 1 2

AVRxm 1 2

AVRxt 1 2

AVRrc 1 2

i) If the condition is false.

ii) If the condition is true.

6.26 BRTC – Branch if the T Bit is Cleared

6.26.1 Description

Conditional relative branch. Tests the T bit and branches relatively to the PC if T is cleared. This instruction branches

relatively to the PC in either direction (PC - 63 ≤ destination ≤ PC + 64). Parameter k is the offset from the PC and is

represented in two’s complement form. (Equivalent to instruction BRBC 6,k.)

Operation:

(i) If T == 0 then PC ← PC + k + 1, else PC ← PC + 1

Syntax: Operands: Program Counter:

(i) BRTC k -64 ≤ k ≤ +63 PC ← PC + k + 1

PC ← PC + 1, if the condition is

false

16-bit Opcode:

1111 01kk kkkk k110

6.26.2 Status Register (SREG) and Boolean Formula

I T H S V N Z C

– – – – – – – –

Example:

bst r3,5 ; Store bit 5 of r3 in T bit

brtc tclear ; Branch if this bit was cleared

...

tclear: nop ; Branch destination (do nothing)

Words 1 (2 bytes)

AVR® Instruction Set Manual

Instruction Description

Table 6-26. Cycles

Name Cycles

i ii

AVRe 1 2

AVRxm 1 2

AVRxt 1 2

AVRrc 1 2

i) If the condition is false.

ii) If the condition is true.

6.27 BRTS – Branch if the T Bit is Set

6.27.1 Description

Conditional relative branch. Tests the T bit and branches relatively to the PC if T is set. This instruction branches

relatively to the PC in either direction (PC - 63 ≤ destination ≤ PC + 64). Parameter k is the offset from the PC and is

represented in two’s complement form. (Equivalent to instruction BRBS 6,k.)

Operation:

(i) If T == 1 then PC ← PC + k + 1, else PC ← PC + 1

Syntax: Operands: Program Counter:

(i) BRTS k -64 ≤ k ≤ +63 PC ← PC + k + 1

PC ← PC + 1, if the condition is

false

16-bit Opcode:

1111 00kk kkkk k110

6.27.2 Status Register (SREG) and Boolean Formula

I T H S V N Z C

– – – – – – – –

Example:

bst r3,5 ; Store bit 5 of r3 in T bit

brts tset ; Branch if this bit was set

...

tset: nop ; Branch destination (do nothing)

Words 1 (2 bytes)

AVR® Instruction Set Manual

Instruction Description

Table 6-27. Cycles

Name Cycles

i ii

AVRe 1 2

AVRxm 1 2

AVRxt 1 2

AVRrc 1 2

i) If the condition is false.

ii) If the condition is true.

6.28 BRVC – Branch if Overflow Cleared

6.28.1 Description

Conditional relative branch. Tests the Overflow (V) flag and branches relatively to the PC if V is cleared. This

instruction branches relatively to the PC in either direction (PC - 63 ≤ destination ≤ PC + 64). Parameter k is the offset

from the PC and is represented in two’s complement form. (Equivalent to instruction BRBC 3,k.)

Operation:

(i) If V == 0 then PC ← PC + k + 1, else PC ← PC + 1

Syntax: Operands: Program Counter:

(i) BRVC k -64 ≤ k ≤ +63 PC ← PC + k + 1

PC ← PC + 1, if the condition is

false

16-bit Opcode:

1111 01kk kkkk k011

6.28.2 Status Register (SREG) and Boolean Formula

I T H S V N Z C

– – – – – – – –

Example:

add r3,r4 ; Add r4 to r3

brvc noover ; Branch if no overflow

...

noover: nop ; Branch destination (do nothing)

Words 1 (2 bytes)

i) If the condition is false.

ii) If the condition is true.

AVR® Instruction Set Manual

Instruction Description

Table 6-28. Cycles

Name Cycles

i ii

AVRe 1 2

AVRxm 1 2

AVRxt 1 2

AVRrc 1 2

6.29 BRVS – Branch if Overflow Set

6.29.1 Description

Conditional relative branch. Tests the Overflow (V) flag and branches relatively to the PC if V is set. This instruction

branches relatively to the PC in either direction (PC - 63 ≤ destination ≤ PC + 64). Parameter k is the offset from the

PC and is represented in two’s complement form. (Equivalent to instruction BRBS 3,k.)

Operation:

(i) If V == 1 then PC ← PC + k + 1, else PC ← PC + 1

Syntax: Operands: Program Counter:

(i) BRVS k -64 ≤ k ≤ +63 PC ← PC + k + 1

PC ← PC + 1, if the condition is

false

16-bit Opcode:

1111 00kk kkkk k011

6.29.2 Status Register (SREG) and Boolean Formula

I T H S V N Z C

– – – – – – – –

Example:

add r3,r4 ; Add r4 to r3

brvs overfl ; Branch if overflow

...

overfl: nop ; Branch destination (do nothing)

Words 1 (2 bytes)

Table 6-29. Cycles

Name Cycles

i ii

AVRe 1 2

AVRxm 1 2

AVR® Instruction Set Manual

Instruction Description

...........continued

Name Cycles

i ii

AVRxt 1 2

AVRrc 1 2

i) If the condition is false.

ii) If the condition is true.

6.30 BSET – Bit Set in SREG

6.30.1 Description

Sets a single flag or bit in SREG.

Operation:

(i) SREG(s) ← 1

Syntax: Operands: Program Counter:

(i) BSET s 0 ≤ s ≤ 7 PC ← PC + 1

16-bit Opcode:

1001 0100 0sss 1000

6.30.2 Status Register (SREG) and Boolean Formula

I T H S V N Z C

⇔⇔⇔⇔⇔⇔⇔⇔

I If (s == 7) then I ← 1, else unchanged.

T If (s == 6) then T ← 1, else unchanged.

H If (s == 5) then H ← 1, else unchanged.

S If (s == 4) then S ← 1, else unchanged.

V If (s == 3) then V ← 1, else unchanged.

N If (s == 2) then N ← 1, else unchanged.

Z If (s == 1) then Z ← 1, else unchanged.

C If (s == 0) then C ← 1, else unchanged.

Example:

bset 6 ; Set T bit

bset 7 ; Enable interrupt

Words 1 (2 bytes)

AVR® Instruction Set Manual

Instruction Description

Table 6-30. Cycles

Name Cycles

AVRe 1

AVRxm 1

AVRxt 1

AVRrc 1

6.31 BST – Bit Store from Bit in Register to T Bit in SREG

6.31.1 Description

Stores bit b from Rd to the T bit in SREG (Status Register).

Operation:

(i) T ← Rd(b)

Syntax: Operands: Program Counter:

(i) BST Rd,b 0 ≤ d ≤ 31, 0 ≤ b ≤ 7 PC ← PC + 1

16-bit Opcode:

1111 101d dddd 0bbb

6.31.2 Status Register (SREG) and Boolean Formula

I T H S V N Z C

– – – – – – –⇔

T ‘ ’ if bit b in Rd is cleared. Set to ‘ ’ otherwise.0 1

Example:

; Copy bit

bst r1,2 ; Store bit 2 of r1 in T bit

bld r0,4 ; Load T into bit 4 of r0

Words 1 (2 bytes)

Table 6-31. Cycles

Name Cycles

AVRe 1

AVRxm 1

AVRxt 1

AVRrc 1

AVR® Instruction Set Manual

Instruction Description

6.32 CALL – Long Call to a Subroutine

6.32.1 Description

Calls to a subroutine within the entire program memory. The return address (to the instruction after the CALL) will be

stored on the Stack. (See also RCALL.) The Stack Pointer uses a post-decrement scheme during CALL.

This instruction is not available on all devices. Refer to .Appendix A

Operation:

(i) PC ← k Devices with 16-bit PC, 128 KB program memory maximum.

(ii) PC ← k Devices with 22-bit PC, 8 MB program memory maximum.

Syntax: Operands: Program Counter: Stack:

(i) CALL k 0 ≤ k < 64K PC ← k STACK ← PC+2

SP ← SP-2, (2 bytes, 16

bits)

(ii) CALL k 0 ≤ k < 4M PC ← k STACK ← PC+2

SP ← SP-3 (3 bytes, 22

bits)

32-bit Opcode:

1001 010k kkkk 111k

kkkk kkkk kkkk kkkk

6.32.2 Status Register (SREG) and Boolean Formula

I T H S V N Z C

– – – – – – – –

Example:

mov r16,r0 ; Copy r0 to r16

call check ; Call subroutine

nop ; Continue (do nothing)

...

check:

cpi r16,0x42 ; Check if r16 has a special value

breq error ; Branch if equal

ret ; Return from subroutine

...

error:

rjmp error ; Infinite loop

Words 2 (4 bytes)

Table 6-32. Cycles

Name Cycles

16-bit PC 22-bit PC

AVRe 4 (1) 5(1)

AVRxm 3 (1) 4(1)

AVR® Instruction Set Manual

Instruction Description

...........continued

Name Cycles

16-bit PC 22-bit PC

AVRxt 3 4

AVRrc N/A N/A

Note:

1. Cycle times for data memory access assume internal RAM access and are not valid for accessing external

RAM.

6.33 CBI – Clear Bit in I/O Register

6.33.1 Description

Clears a specified bit in an I/O Register. This instruction operates on the lower 32 I/O Registers – addresses 0-31.

Operation:

(i) I/O(A,b) ← 0

Syntax: Operands: Program Counter:

(i) CBI A,b 0 ≤ A ≤ 31, 0 ≤ b ≤ 7 PC ← PC + 1

16-bit Opcode:

1001 1000 AAAA Abbb

6.33.2 Status Register (SREG) and Boolean Formula

I T H S V N Z C

– – – – – – – –

Example:

cbi 0x12,7 ; Clear bit 7 at address 0x12

Words 1 (2 bytes)

Table 6-33. Cycles

Name Cycles

AVRe 2

AVRxm 1

AVRxt 1

AVRrc 1

AVR® Instruction Set Manual

Instruction Description

6.34 CBR – Clear Bits in Register

6.34.1 Description

Clears the specified bits in register Rd. Performs the logical AND between the contents of register Rd and the

complement of the constant mask K. The result will be placed in register Rd. (Equivalent to ANDI Rd,(0xFF - K).)

Operation:

(i) Rd ← Rd (0xFF - K)∧

Syntax: Operands: Program Counter:

(i) CBR Rd,K 16 ≤ d ≤ 31, 0 ≤ K ≤ 255 PC ← PC + 1

16-bit Opcode: (see ANDI with K complemented)

6.34.2 Status Register (SREG) and Boolean Formula

I T H S V N Z C

– – – 0 –⇔ ⇔ ⇔

SN V, for signed tests.⊕

Cleared.

NR7

Set if MSB of the result is set; cleared otherwise.

ZR7 R6 R5 R4 R3 R2 R1 R0∧∧∧∧∧∧∧

Set if the result is ; cleared otherwise.0x00

R (Result) equals Rd after the operation.

Example:

cbr r16,0xF0 ; Clear upper nibble of r16

cbr r18,1 ; Clear bit 0 in r18

Words 1 (2 bytes)

Table 6-34. Cycles

Name Cycles

AVRe 1

AVRxm 1

AVRxt 1

AVRrc 1

AVR® Instruction Set Manual

Instruction Description

6.35 CLC – Clear Carry Flag

6.35.1 Description

Clears the Carry (C) flag in SREG (Status Register). (Equivalent to instruction BCLR 0.)

Operation:

(i) C ← 0

Syntax: Operands: Program Counter:

(i) CLC None PC ← PC + 1

16-bit Opcode:

1001 0100 1000 1000

6.35.2 Status Register (SREG) and Boolean Formula

I T H S V N Z C

– – – – – – – 0

Carry flag cleared.

Example:

add r0,r0 ; Add r0 to itself

clc ; Clear Carry flag

Words 1 (2 bytes)

Table 6-35. Cycles

Name Cycles

AVRe 1

AVRxm 1

AVRxt 1

AVRrc 1

6.36 CLH – Clear Half Carry Flag

6.36.1 Description

Clears the Half Carry (H) flag in SREG (Status Register). (Equivalent to instruction BCLR 5.)

Operation:

(i) H ← 0

Syntax: Operands: Program Counter:

AVR® Instruction Set Manual

Instruction Description

(i) CLH None PC ← PC + 1

16-bit Opcode:

1001 0100 1101 1000

6.36.2 Status Register (SREG) and Boolean Formula

I T H S V N Z C

– – 0 – – – – –

Half Carry flag cleared.

Example:

clh ; Clear the Half Carry flag

Words 1 (2 bytes)

Table 6-36. Cycles

Name Cycles

AVRe 1

AVRxm 1

AVRxt 1

AVRrc 1

6.37 CLI – Clear Global Interrupt Enable Bit

6.37.1 Description

Clears the Global Interrupt Enable (I) bit in SREG (Status Register). The interrupts will be immediately disabled.

No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction.

(Equivalent to instruction BCLR 7.)

Operation:

(i) I ← 0

Syntax: Operands: Program Counter:

(i) CLI None PC ← PC + 1

16-bit Opcode:

1001 0100 1111 1000

6.37.2 Status Register (SREG) and Boolean Formula

I T H S V N Z C

0 – – – – – – –

AVR® Instruction Set Manual

Instruction Description

Global Interrupt Enable bit cleared.

Example:

in temp, SREG ; Store SREG value (temp must be defined by user)

cli ; Disable interrupts during timed sequence

sbi EECR, EEMWE ; Start EEPROM write

sbi EECR, EEWE

out SREG, temp ; Restore SREG value (I-flag)

Words 1 (2 bytes)

Table 6-37. Cycles

Name Cycles

AVRe 1

AVRxm 1

AVRxt 1

AVRrc 1

6.38 CLN – Clear Negative Flag

6.38.1 Description

Clears the Negative (N) flag in SREG (Status Register). (Equivalent to instruction BCLR 2.)

Operation:

(i) N ← 0

Syntax: Operands: Program Counter:

(i) CLN None PC ← PC + 1

16-bit Opcode:

1001 0100 1010 1000

6.38.2 Status Register (SREG) and Boolean Formula

I T H S V N Z C

– – – – – 0 – –

Negative flag cleared.

Example:

add r2,r3 ; Add r3 to r2

cln ; Clear Negative flag

Words 1 (2 bytes)

AVR® Instruction Set Manual

Instruction Description

Table 6-38. Cycles

Name Cycles

AVRe 1

AVRxm 1

AVRxt 1

AVRrc 1

6.39 CLR – Clear Register

6.39.1 Description

Clears a register. This instruction performs an Exclusive OR between a register and itself. This will clear all bits in the

Operation:

(i) Rd ← Rd Rd⊕

Syntax: Operands: Program Counter:

(i) CLR Rd 0 ≤ d ≤ 31 PC ← PC + 1

16-bit Opcode: (see EOR Rd,Rd)

0010 01dd dddd dddd

6.39.2 Status Register (SREG) and Boolean Formula

I T H S V N Z C

– – – 0 0 0 1 –

Cleared.

Set.

R (Result) equals Rd after the operation.

Example:

clr r18 ; clear r18

loop: inc r18 ; increase r18

...

cpi r18,0x50 ; Compare r18 to 0x50

brne loop

AVR® Instruction Set Manual

Instruction Description

Words 1 (2 bytes)

Table 6-39. Cycles

Name Cycles

AVRe 1

AVRxm 1

AVRxt 1

AVRrc 1

6.40 CLS – Clear Sign Flag

6.40.1 Description

Clears the Sign (S) flag in SREG (Status Register). (Equivalent to instruction BCLR 4.)

Operation:

(i) S ← 0

Syntax: Operands: Program Counter:

(i) CLS None PC ← PC + 1

16-bit Opcode:

1001 0100 1100 1000

6.40.2 Status Register (SREG) and Boolean Formula

I T H S V N Z C

– – – 0 – – – –

Sign flag cleared.

Example:

add r2,r3 ; Add r3 to r2

cls ; Clear Sign flag

Words 1 (2 bytes)

Table 6-40. Cycles

Name Cycles

AVRe 1

AVRxm 1

AVRxt 1

AVRrc 1

AVR® Instruction Set Manual

Instruction Description

6.41 CLT – Clear T Bit

6.41.1 Description

Clears the T bit in SREG (Status Register). (Equivalent to instruction BCLR 6.)

Operation:

(i) T ← 0

Syntax: Operands: Program Counter:

(i) CLT None PC ← PC + 1

16-bit Opcode:

1001 0100 1110 1000

6.41.2 Status Register (SREG) and Boolean Formula

I T H S V N Z C

– 0 – – – – – –

T bit cleared.

Example:

clt ; Clear T bit

Words 1 (2 bytes)

Table 6-41. Cycles

Name Cycles

AVRe 1

AVRxm 1

AVRxt 1

AVRrc 1

6.42 CLV – Clear Overflow Flag

6.42.1 Description

Clears the Overflow (V) flag in SREG (Status Register). (Equivalent to instruction BCLR 3.)

Operation:

(i) V ← 0

Syntax: Operands: Program Counter:

(i) CLV None PC ← PC + 1

AVR® Instruction Set Manual

Instruction Description

16-bit Opcode:

1001 0100 1011 1000

6.42.2 Status Register (SREG) and Boolean Formula

I T H S V N Z C

– – – – 0 – – –

Overflow flag cleared.

Example:

add r2,r3 ; Add r3 to r2

clv ; Clear Overflow flag

Words 1 (2 bytes)

Table 6-42. Cycles

Name Cycles

AVRe 1

AVRxm 1

AVRxt 1

AVRrc 1

6.43 CLZ – Clear Zero Flag

6.43.1 Description

Clears the Zero (Z) flag in SREG (Status Register). (Equivalent to instruction BCLR 1.)

Operation:

(i) Z ← 0

Syntax: Operands: Program Counter:

(i) CLZ None PC ← PC + 1

16-bit Opcode:

1001 0100 1001 1000

6.43.2 Status Register (SREG) and Boolean Formula

I T H S V N Z C

– – – – – – 0 –

AVR® Instruction Set Manual

Instruction Description

Zero flag cleared.

Example:

add r2,r3 ; Add r3 to r2

clz ; Clear zero

Words 1 (2 bytes)

Table 6-43. Cycles

Name Cycles

AVRe 1

AVRxm 1

AVRxt 1

AVRrc 1

6.44 COM – One’s Complement

6.44.1 Description

This instruction performs a One’s Complement of register Rd.

Operation:

(i) Rd ← 0xFF - Rd

Syntax: Operands: Program Counter:

(i) COM Rd 0 ≤ d ≤ 31 PC ← PC + 1

16-bit Opcode:

1001 010d dddd 0000

6.44.2 Status Register (SREG) and Boolean Formula

I T H S V N Z C

– – – 0 1⇔ ⇔ ⇔

SN V, for signed tests.⊕

Cleared.

NR7

Set if MSB of the result is set; cleared otherwise.

ZR7 R6 R5 R4 R3 R2 R1 R0∧∧∧∧∧∧∧

Set if the result is ; cleared otherwise.0x00

AVR® Instruction Set Manual

Instruction Description

Set.

R (Result) equals Rd after the operation.

Example:

com r4 ; Take one’s complement of r4

breq zero ; Branch if zero

...

zero: nop ; Branch destination (do nothing)

Words 1 (2 bytes)

Table 6-44. Cycles

Name Cycles

AVRe 1

AVRxm 1

AVRxt 1

AVRrc 1

6.45 CP – Compare

6.45.1 Description

This instruction performs a compare between two registers Rd and Rr. None of the registers are changed. All

conditional branches can be used after this instruction.

Operation:

(i) Rd - Rr

Syntax: Operands: Program Counter:

(i) CP Rd,Rr 0 ≤ d ≤ 31, 0 ≤ r ≤ 31 PC ← PC + 1

16-bit Opcode:

0001 01rd dddd rrrr

6.45.2 Status Register (SREG) and Boolean Formula

I T H S V N Z C

– – ⇔⇔⇔⇔⇔⇔

HRd3 Rr3 Rr3 R3 R3 Rd3∧ ∨ ∧ ∨ ∧

Set if there was a borrow from bit 3; cleared otherwise.

SN V, for signed tests.⊕

VRd7 Rr7 R7 Rd7 Rr7 R7∧ ∧ ∨ ∧ ∧

Set if two’s complement overflow resulted from the operation; cleared otherwise.

NR7

AVR® Instruction Set Manual

Instruction Description

Set if MSB of the result is set; cleared otherwise.

ZR7 R6 R5 R4 R3 R2 R1 R0∧∧∧∧∧∧∧

Set if the result is ; cleared otherwise.0x00

CRd7 Rr7 Rr7 R7 R7 Rd7∧ ∨ ∧ ∨ ∧

Set if the absolute value of the contents of Rr is larger than the absolute value of Rd; cleared otherwise.

R (Result) after the operation.

Example:

cp r4,r19 ; Compare r4 with r19

brne noteq ; Branch if r4 <> r19

...

noteq:

nop ; Branch destination (do nothing)

Words 1 (2 bytes)

Table 6-45. Cycles

Name Cycles

AVRe 1

AVRxm 1

AVRxt 1

AVRrc 1

6.46 CPC – Compare with Carry

6.46.1 Description

This instruction performs a compare between two registers Rd and Rr and also takes into account the previous carry.

None of the registers are changed. All conditional branches can be used after this instruction.

Operation:

(i) Rd - Rr - C

Syntax: Operands: Program Counter:

(i) CPC Rd,Rr 0 ≤ d ≤ 31, 0 ≤ r ≤ 31 PC ← PC + 1

16-bit Opcode:

0000 01rd dddd rrrr

6.46.2 Status Register (SREG) and Boolean Formula

I T H S V N Z C

– – ⇔⇔⇔⇔⇔⇔

HRd3 Rr3 Rr3 R3 R3 Rd3∧ ∨ ∧ ∨ ∧

AVR® Instruction Set Manual

Instruction Description

Set if there was a borrow from bit 3; cleared otherwise.

SN V, for signed tests.⊕

VRd7 Rr7 R7 Rd7 Rr7 R7∧ ∧ ∨ ∧ ∧

Set if two’s complement overflow resulted from the operation; cleared otherwise.

NR7

Set if MSB of the result is set; cleared otherwise.

ZR7 R6 R5 R4 R3 R2 R1 R0 Z∧∧∧∧∧∧∧∧

The previous value remains unchanged when the result is zero; cleared otherwise.

CRd7 Rr7 Rr7 R7 R7 Rd7∧ ∨ ∧ ∨ ∧

Set if the absolute value of the contents of Rr plus previous carry is larger than the absolute value of Rd; cleared

otherwise.

R (Result) after the operation.

Example:

; Compare r3:r2 with r1:r0

cp r2,r0 ; Compare low byte

cpc r3,r1 ; Compare high byte

brne noteq ; Branch if not equal

...

noteq:

nop ; Branch destination (do nothing)

Words 1 (2 bytes)

Table 6-46. Cycles

Name Cycles

AVRe 1

AVRxm 1

AVRxt 1

AVRrc 1

6.47 CPI – Compare with Immediate

6.47.1 Description

This instruction performs a compare between register Rd and a constant. The register is not changed. All conditional

branches can be used after this instruction.

Operation:

(i) Rd - K

Syntax: Operands: Program Counter:

(i) CPI Rd,K 16 ≤ d ≤ 31, 0 ≤ K ≤ 255 PC ← PC + 1

16-bit Opcode:

AVR® Instruction Set Manual

Instruction Description

check: cpi r16,0x11 ; Compare r16 to 0x11

...

cpi r17,0x32 ; Compare r17 to 0x32

...

ret ; Return from subroutine

Words 1 (2 bytes)

Table 6-76. Cycles

Name Cycles

AVRe 1

AVRxm 1

AVRxt 1

AVRrc N/A

6.77 MUL – Multiply Unsigned

6.77.1 Description

This instruction performs 8-bit × 8-bit → 16-bit unsigned multiplication.

Rd Rr R1 R0

Multiplicand ×Multiplier →Product High Product Low

8 8 16

The multiplicand Rd and the multiplier Rr are two registers containing unsigned numbers. The 16-bit unsigned

product is placed in R1 (high byte) and R0 (low byte). Note that if the multiplicand or the multiplier is selected from R0

or R1, the result will overwrite those after multiplication.

This instruction is not available on all devices. Refer to .Appendix A

Operation:

(i) R1:R0 ← Rd × Rr (unsigned ← unsigned × unsigned)

Syntax: Operands: Program Counter:

(i) MUL Rd,Rr 0 ≤ d ≤ 31, 0 ≤ r ≤ 31 PC ← PC + 1

16-bit Opcode:

1001 11rd dddd rrrr

6.77.2 Status Register (SREG) and Boolean Formula

I T H S V N Z C

––––––⇔ ⇔

C R15

Z R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0∧ ∧ ∧ ∧ ∧ ∧ ∧ ∧ ∧ ∧ ∧ ∧ ∧ ∧ ∧

Set if the result is ; cleared otherwise.0x0000

R (Result) equals R1,R0 after the operation.

AVR® Instruction Set Manual

Instruction Description

Example:

mul r5,r4 ; Multiply unsigned r5 and r4

movw r4,r0 ; Copy result back in r5:r4

Words 1 (2 bytes)

Table 6-77. Cycles

Name Cycles

AVRe 2

AVRxm 2

AVRxt 2

AVRrc N/A

6.78 MULS – Multiply Signed

6.78.1 Description

This instruction performs 8-bit × 8-bit → 16-bit signed multiplication.

Rd Rr R1 R0

Multiplicand × Multiplier → Product High Product Low

8 8 16

The multiplicand Rd and the multiplier Rr are two registers containing signed numbers. The 16-bit signed product is

placed in R1 (high byte) and R0 (low byte).

This instruction is not available on all devices. Refer to .Appendix A

Operation:

(i) R1:R0 ← Rd × Rr (signed ← signed × signed)

Syntax: Operands: Program Counter:

(i) MULS Rd,Rr 16 ≤ d ≤ 31, 16 ≤ r ≤ 31 PC ← PC + 1

16-bit Opcode:

0000 0010 dddd rrrr

6.78.2 Status Register (SREG) and Boolean Formula

I T H S V N Z C

– – – – – – ⇔ ⇔

C R15

Z R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0∧ ∧ ∧ ∧ ∧ ∧ ∧ ∧ ∧ ∧ ∧ ∧ ∧ ∧ ∧

Set if the result is ; cleared otherwise.0x0000

R (Result) equals R1,R0 after the operation.

AVR® Instruction Set Manual

Instruction Description

Example:

muls r21,r20 ; Multiply signed r21 and r20

movw r20,r0 ; Copy result back in r21:r20

Words 1 (2 bytes)

Table 6-78. Cycles

Name Cycles

AVRe 2

AVRxm 2

AVRxt 2

AVRrc N/A

6.79 MULSU – Multiply Signed with Unsigned

6.79.1 Description

This instruction performs 8-bit × 8-bit → 16-bit multiplication of a signed and an unsigned number.

Rd Rr R1 R0

Multiplicand Multiplier → Product High Product Low

8 8 16

The multiplicand Rd and the multiplier Rr are two registers. The multiplicand Rd is a signed number, and the

multiplier Rr is unsigned. The 16-bit signed product is placed in R1 (high byte) and R0 (low byte).

This instruction is not available on all devices. Refer to .Appendix A

Operation:

(i) R1:R0 ← Rd × Rr (signed ← signed × unsigned)

Syntax: Operands: Program Counter:

(i) MULSU Rd,Rr 16 ≤ d ≤ 23, 16 ≤ r ≤ 23 PC ← PC + 1

16-bit Opcode:

0000 0011 0ddd 0rrr

6.79.2 Status Register (SREG) and Boolean Formula

I T H S V N Z C

– – – – – – ⇔ ⇔

C R15

Z R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0∧ ∧ ∧ ∧ ∧ ∧ ∧ ∧ ∧ ∧ ∧ ∧ ∧ ∧ ∧

Set if the result is ; cleared otherwise.0x0000

R (Result) equals R1,R0 after the operation.

AVR® Instruction Set Manual

Instruction Description

Example:

;******************************************************************************

;* DESCRIPTION

;* Signed multiply of two 16-bit numbers with 32-bit result.

;* USAGE

;* r19:r18:r17:r16 = r23:r22 * r21:r20

;******************************************************************************

muls16x16_32:

clr r2

muls r23, r21 ; (signed)ah * (signed)bh

movw r18, r0

mul r22, r20 ; al * bl

movw r16, r0

mulsu r23, r20 ; (signed)ah * bl

sbc r19, r2

add r17, r0

adc r18, r1

adc r19, r2

mulsu r21, r22 ; (signed)bh * al

sbc r19, r2

add r17, r0

adc r18, r1

adc r19, r2

ret

Words 1 (2 bytes)

Table 6-79. Cycles

Name Cycles

AVRe 2

AVRxm 2

AVRxt 2

AVRrc N/A

6.80 NEG – Two’s Complement

6.80.1 Description

Replaces the contents of register Rd with its two’s complement; the value is left unchanged.0x80

Operation:

(i) Rd ← - Rd0x00

Syntax: Operands: Program Counter:

(i) NEG Rd 0 ≤ d ≤ 31 PC ← PC + 1

16-bit Opcode:

1001 010d dddd 0001

6.80.2 Status Register (SREG) and Boolean Formula

I T H S V N Z C

– – ⇔⇔⇔⇔⇔⇔

AVR® Instruction Set Manual

Instruction Description

H R3 Rd3∨

Set if there was a borrow from bit 3; cleared otherwise.

S N V, for signed tests.⊕

V R7 R6 R5 R4 R3 R2 R1 R0∧∧∧∧∧∧∧

Set if there is a two’s complement overflow from the implied subtraction from zero; cleared otherwise. A two’s

complement overflow will occur only if the contents of the Register after the operation (Result) is .0x80

N R7

Set if MSB of the result is set; cleared otherwise.

Z R7 R6 R5 R4 R3 R2 R1 R0∧∧∧∧∧∧∧

Set if the result is ; cleared otherwise.0x00

C R7 R6 R5 R4 R3 R2 R1 R0∨∨∨∨∨∨∨

Set if there is a borrow in the implied subtraction from zero; cleared otherwise. The C flag will be set in all cases

except when the contents of the Register after the operation is .0x00

R (Result) equals Rd after the operation.

Example:

sub r11,r0 ; Subtract r0 from r11

brpl positive ; Branch if result positive

neg r11 ; Take two’s complement of r11

positive:

nop ; Branch destination (do nothing)

Words 1 (2 bytes)

Table 6-80. Cycles

Name Cycles

AVRe 1

AVRxm 1

AVRxt 1

AVRrc 1

6.81 NOP – No Operation

6.81.1 Description

This instruction performs a single cycle No Operation.

Operation:

(i) No

Syntax: Operands: Program Counter:

(i) NOP None PC ← PC + 1

16-bit Opcode:

AVR® Instruction Set Manual

Instruction Description

0000 0000 0000 0000

6.81.2 Status Register (SREG) and Boolean Formula

I T H S V N Z C

– – – – – – – –

Example:

clr r16 ; Clear r16

ser r17 ; Set r17

out 0x18,r16 ; Write zeros to Port B

nop ; Wait (do nothing)

out 0x18,r17 ; Write ones to Port B

Words 1 (2 bytes)

Table 6-81. Cycles

Name Cycles

AVRe 1

AVRxm 1

AVRxt 1

AVRrc 1

6.82 OR – Logical OR

6.82.1 Description

Performs the logical OR between the contents of register Rd and register Rr, and places the result in the destination

Operation:

(i) Rd ← Rd v Rr

Syntax: Operands: Program Counter:

(i) OR Rd,Rr 0 ≤ d ≤ 31, 0 ≤ r ≤ 31 PC ← PC + 1

16-bit Opcode:

0010 10rd dddd rrrr

6.82.2 Status Register (SREG) and Boolean Formula

I T H S V N Z C

– – – 0 –⇔ ⇔ ⇔

S N V, for signed tests.⊕

V 0

Cleared.

AVR® Instruction Set Manual

Instruction Description

N R7

Set if MSB of the result is set; cleared otherwise.

Z R7 R6 R5 R4 R3 R2 R1 R0∧∧∧∧∧∧∧

Set if the result is ; cleared otherwise.0x00

R (Result) equals Rd after the operation.

Example:

or r15,r16 ; Do bitwise or between registers

bst r15,6 ; Store bit 6 of r15 in T bit

brts ok ; Branch if T bit set

...

ok:

nop ; Branch destination (do nothing)

Words 1 (2 bytes)

Table 6-82. Cycles

Name Cycles

AVRe 1

AVRxm 1

AVRxt 1

AVRrc 1

6.83 ORI – Logical OR with Immediate

6.83.1 Description

Performs the logical OR between the contents of register Rd and a constant, and places the result in the destination

Operation:

(i) Rd ← Rd v K

Syntax: Operands: Program Counter:

(i) ORI Rd,K 16 ≤ d ≤ 31, 0 ≤ K ≤ 255 PC ← PC + 1

16-bit Opcode:

0110 KKKK dddd KKKK

6.83.2 Status Register (SREG) and Boolean Formula

I T H S V N Z C

– – – 0 –⇔ ⇔ ⇔

S N V, for signed tests.⊕

V 0

AVR® Instruction Set Manual

Instruction Description

Cleared.

N R7

Set if MSB of the result is set; cleared otherwise.

Z R7 R6 R5 R4 R3 R2 R1 R0∧∧∧∧∧∧∧

Set if the result is ; cleared otherwise.0x00

R (Result) equals Rd after the operation.

Example:

ori r16,0xF0 ; Set high nibble of r16

ori r17,1 ; Set bit 0 of r17

Words 1 (2 bytes)

Table 6-83. Cycles

Name Cycles

AVRe 1

AVRxm 1

AVRxt 1

AVRrc 1

6.84 OUT – Store Register to I/O Location

6.84.1 Description

Stores data from register Rr in the Register File to I/O space.

Operation:

(i) I/O(A) ← Rr

Syntax: Operands: Program Counter:

(i) OUT A,Rr 0 ≤ r ≤ 31, 0 ≤ A ≤ 63 PC ← PC + 1

16-bit Opcode:

1011 1AAr rrrr AAAA

6.84.2 Status Register (SREG) and Boolean Formula

I T H S V N Z C

– – – – – – – –

Example:

clr r16 ; Clear r16

ser r17 ; Set r17

out 0x18,r16 ; Write zeros to Port B

AVR® Instruction Set Manual

Instruction Description

nop ; Wait (do nothing)

out 0x18,r17 ; Write ones to Port B

Words 1 (2 bytes)

Table 6-84. Cycles

Name Cycles

AVRe 1

AVRxm 1

AVRxt 1

AVRrc 1

6.85 POP – Pop Register from Stack

6.85.1 Description

This instruction loads register Rd with a byte from the STACK. The Stack Pointer is pre-incremented by 1 before the

POP.

This instruction is not available on all devices. Refer to .Appendix A

Operation:

(i) Rd ← STACK

Syntax: Operands: Program Counter: Stack:

(i) POP Rd 0 ≤ d ≤ 31 PC ← PC + 1 SP ← SP + 1

16-bit Opcode:

1001 000d dddd 1111

6.85.2 Status Register (SREG) and Boolean Formula

I T H S V N Z C

– – – – – – – –

Example:

call routine ; Call subroutine

...

routine:

push r14 ; Save r14 on the Stack

push r13 ; Save r13 on the Stack

...

pop r13 ; Restore r13

pop r14 ; Restore r14

ret ; Return from subroutine

Words 1 (2 bytes)

AVR® Instruction Set Manual

Instruction Description

Table 6-85. Cycles

Name Cycles

AVRe 2

AVRxm 2(1)

AVRxt 2

AVRrc 3

Note:

1. Cycle times for data memory access assume internal RAM access and are not valid for accessing external

RAM.

6.86 PUSH – Push Register on Stack

6.86.1 Description

This instruction stores the contents of register Rr on the STACK. The Stack Pointer is post-decremented by 1 after

the PUSH.

This instruction is not available on all devices. Refer to .Appendix A

Operation:

(i) STACK ← Rr

Syntax: Operands: Program Counter: Stack:

(i) PUSH Rr 0 ≤ r ≤ 31 PC ← PC + 1 SP ← SP - 1

16-bit Opcode:

1001 001d dddd 1111

6.86.2 Status Register (SREG) and Boolean Formula

I T H S V N Z C

– – – – – – – –

Example:

call routine ; Call subroutine

...

routine:

push r14 ; Save r14 on the Stack

push r13 ; Save r13 on the Stack

...

pop r13 ; Restore r13

pop r14 ; Restore r14

ret ; Return from subroutine

Words 1 (2 bytes)

AVR® Instruction Set Manual

Instruction Description

Table 6-86. Cycles

Name Cycles

AVRe 2

AVRxm 1(1)

AVRxt 1

AVRrc 1

Note:

1. Cycle times for data memory access assume internal RAM access and are not valid for accessing external

RAM.

6.87 RCALL – Relative Call to Subroutine

6.87.1 Description

Relative call to an address within PC - 2K + 1 and PC + 2K (words). The return address (the instruction after the

RCALL) is stored onto the Stack. See also CALL. For AVR microcontrollers with program memory not exceeding 4K

words (8 KB), this instruction can address the entire memory from every address location. The Stack Pointer uses a

post-decrement scheme during RCALL.

Operation: Comment:

(i) PC ← PC + k + 1 Devices with 16-bit PC, 128 KB program memory maximum.

(ii) PC ← PC + k + 1 Devices with 22-bit PC, 8 MB program memory maximum.

Syntax: Operands: Program Counter: Stack:

(i) RCALL k -2K ≤ k < 2K PC ← PC + k + 1 STACK ← PC + 1

SP ← SP - 2 (2 bytes, 16

bits)

(ii) RCALL k -2K ≤ k < 2K PC ← PC + k + 1 STACK ← PC + 1

SP ← SP - 3 (3 bytes, 22

bits)

16-bit Opcode:

1101 kkkk kkkk kkkk

6.87.2 Status Register (SREG) and Boolean Formula

I T H S V N Z C

– – – – – – – –

Example:

rcall routine ; Call subroutine

...

routine:

push r14 ; Save r14 on the Stack

...

pop r14 ; Restore r14

ret ; Return from subroutine

AVR® Instruction Set Manual

Instruction Description

Words 1 (2 bytes)

Table 6-87. Cycles

Name Cycles

9/16-bit PC 22-bit PC

AVRe 3 (1) 4(1)

AVRxm 2 (1) 3(1)

AVRxt 2 3

AVRrc 3 N/A

Note:

1. Cycle times for data memory access assume internal RAM access and are not valid for accessing external

RAM.

6.88 RET – Return from Subroutine

6.88.1 Description

Returns from the subroutine. The return address is loaded from the STACK. The Stack Pointer uses a pre-increment

scheme during RET.

Operation:

Operation: Comment:

(i) PC(15:0) ← STACK Devices with 16-bit PC, 128 KB program memory maximum.

(ii) PC(21:0) ← STACK Devices with 22-bit PC, 8 MB program memory maximum.

Syntax: Operands: Program Counter: Stack:

(i) RET None See Operation SP ← SP + 2, (2 bytes,16

bits)

(ii) RET None See Operation SP ← SP + 3, (3 bytes,22

bits)

16-bit Opcode:

1001 0101 0000 1000

6.88.2 Status Register (SREG) and Boolean Formula

I T H S V N Z C

– – – – – – – –

Example:

call routine ; Call subroutine

...

routine:

push r14 ; Save r14 on the Stack

...

pop r14 ; Restore r14

ret ; Return from subroutine

AVR® Instruction Set Manual

Instruction Description

Words 1 (2 bytes)

Table 6-88. Cycles

Name Cycles

9/16-bit PC 22-bit PC

AVRe 4(1) 5(1)

AVRxm 4(1) 5(1)

AVRxt 4 5

AVRrc 6 N/A

Note:

1. Cycle times for data memory access assume internal RAM access and are not valid for accessing external

RAM.

6.89 RETI – Return from Interrupt

6.89.1 Description

Returns from the interrupt. The return address is loaded from the STACK, and the Global Interrupt Enable bit is set.

Note that the Status Register is not automatically stored when entering an interrupt routine, and it is not restored

when returning from an interrupt routine. This must be handled by the application program. The Stack Pointer uses a

pre-increment scheme during RETI.

Operation: Comment:

(i) PC(15:0) ← STACK Devices with 16-bit PC, 128 KB program memory maximum.

(ii) PC(21:0) ← STACK Devices with 22-bit PC, 8 MB program memory maximum.

Syntax: Operands: Program Counter: Stack:

(i) RETI None See Operation SP ← SP + 2 (2 bytes, 16

bits)

(ii) RETI None See Operation SP ← SP + 3 (3 bytes, 22

bits)

16-bit Opcode:

1001 0101 0001 1000

6.89.2 Status Register (SREG) and Boolean Formula

I T H S V N Z C

1 – – – – – – –

The I flag is set.

Example:

...

AVR® Instruction Set Manual

Instruction Description

extint:

push r0 ; Save r0 on the Stack

...

pop r0 ; Restore r0

reti ; Return and enable interrupts

Words 1 (2 bytes)

Table 6-89. Cycles

Name Cycles

9/16-bit PC 22-bit PC

AVRe 4(2) 5(2)

AVRxm 4(2) 5(2)

AVRxt 4 5

AVRrc 6 N/A

Notes:

1. RETI behaves differently in AVRe, AVRxm, and AVRxt devices. In the AVRe series of devices, the Global

Interrupt Enable bit is cleared by hardware once an interrupt occurs, and this bit is set when RETI is executed.

In the AVRxm and AVRxt devices, RETI will not modify the Global Interrupt Enable bit in SREG since it is

not cleared by hardware while entering ISR. This bit should be modified using SEI and CLI instructions when

needed.

2. Cycle times for data memory access assume internal RAM access and are not valid for accessing external

RAM.

6.90 RJMP – Relative Jump

6.90.1 Description

Relative jump to an address within PC - 2K +1 and PC + 2K (words). For AVR microcontrollers with pogram memory

not exceeding 4K words (8 KB), this instruction can address the entire memory from every address location. See also

JMP.

Operation:

(i) PC ← PC + k + 1

Syntax: Operands: Program Counter: Stack:

(i) RJMP k -2K ≤ k < 2K PC ← PC + k + 1 Unchanged

16-bit Opcode:

1100 kkkk kkkk kkkk

6.90.2 Status Register (SREG) and Boolean Formula

I T H S V N Z C

– – – – – – – –

Example:

cpi r16,0x42 ; Compare r16 to 0x42

brne error ; Branch if r16 <> 0x42

AVR® Instruction Set Manual

Instruction Description

rjmp ok ; Unconditional branch

error:

add r16,r17 ; Add r17 to r16

inc r16 ; Increment r16

ok:

nop ; Destination for rjmp (do nothing)

Words 1 (2 bytes)

Table 6-90. Cycles

Name Cycles

AVRe 2

AVRxm 2

AVRxt 2

AVRrc 2

6.91 ROL – Rotate Left trough Carry

6.91.1 Description

Shifts all bits in Rd one place to the left. The C flag is shifted into bit 0 of Rd. Bit 7 is shifted into the C flag. This

operation, combined with LSL, effectively multiplies multi-byte signed and unsigned values by two.

Operation:

←

C ¨ b7 - - - - - - - - - - - - - - - - - - b0 ←C

Syntax: Operands: Program Counter:

(i) ROL Rd 0 ≤ d ≤ 31 PC ← PC + 1

16-bit Opcode: (see ADC Rd,Rd)

0001 11dd dddd dddd

6.91.2 Status Register (SREG) and Boolean Formula

I T H S V N Z C

– – ⇔⇔⇔⇔⇔⇔

HRd3

SN V, for signed tests.⊕

VN C, for N and C after the shift.⊕

NR7

Set if MSB of the result is set; cleared otherwise.

ZR7 R6 R5 R4 R3 R2 R1 R0∧∧∧∧∧∧∧

Set if the result is ; cleared otherwise.0x00

AVR® Instruction Set Manual

Instruction Description

CRd7

Set if, before the shift, the MSB of Rd was set; cleared otherwise.

R (Result) equals Rd after the operation.

Example:

lsl r18 ; Multiply r19:r18 by two

rol r19 ; r19:r18 is a signed or unsigned two-byte integer

brcs oneenc ; Branch if carry set

...

oneenc:

nop ; Branch destination (do nothing)

Words 1 (2 bytes)

Table 6-91. Cycles

Name Cycles

AVRe 1

AVRxm 1

AVRxt 1

AVRrc 1

6.92 ROR – Rotate Right through Carry

6.92.1 Description

Shifts all bits in Rd one place to the right. The C flag is shifted into bit 7 of Rd. Bit 0 is shifted into the C flag. This

operation, combined with ASR, effectively divides multi-byte signed values by two. Combined with LSR, it effectively

divides multi-byte unsigned values by two. The Carry flag can be used to round the result.

Operation:

→

C→b7 - - - - - - - - - - - - - - - - - - b0 →C

Syntax: Operands: Program Counter:

(i) ROR Rd 0 ≤ d ≤ 31 PC ← PC + 1

16-bit Opcode:

1001 010d dddd 0111

6.92.2 Status Register (SREG) and Boolean Formula

I T H S V N Z C

–––⇔⇔⇔⇔⇔

SN V, for signed tests.⊕

VN C, for N and C after the shift.⊕

AVR® Instruction Set Manual

Instruction Description

NR7

Set if MSB of the result is set; cleared otherwise.

ZR7 R6 R5 R4 R3 R2 R1 R0∧∧∧∧∧∧∧

Set if the result is ; cleared otherwise.0x00

CRd0

Set if, before the shift, the LSB of Rd was set; cleared otherwise.

R (Result) equals Rd after the operation.

Example:

lsr r19 ; Divide r19:r18 by two

ror r18 ; r19:r18 is an unsigned two-byte integer

brcc zeroenc1 ; Branch if carry cleared

asr r17 ; Divide r17:r16 by two

ror r16 ; r17:r16 is a signed two-byte integer

brcc zeroenc2 ; Branch if carry cleared

...

zeroenc1:

nop ; Branch destination (do nothing)

...

zeroenc1:

nop ; Branch destination (do nothing)

Words 1 (2 bytes)

Table 6-92. Cycles

Name Cycles

AVRe 1

AVRxm 1

AVRxt 1

AVRrc 1

6.93 SBC – Subtract with Carry

6.93.1 Description

Subtracts two registers and subtracts with the C flag, and places the result in the destination register Rd.

Operation:

(i) Rd ← Rd - Rr - C

Syntax: Operands: Program Counter:

(i) SBC Rd,Rr 0 ≤ d ≤ 31, 0 ≤ r ≤ 31 PC ← PC + 1

16-bit Opcode:

0000 10rd dddd rrrr

AVR® Instruction Set Manual

Instruction Description

6.93.2 Status Register (SREG) and Boolean Formula

I T H S V N Z C

– – ⇔⇔⇔⇔⇔⇔

HRd3 Rr3 Rr3 R3 R3 Rd3∧ ∨ ∧ ∨ ∧

Set if there was a borrow from bit 3; cleared otherwise.

SN V, for signed tests.⊕

VRd7 Rr7 R7 Rd7 Rr7 R7∧ ∧ ∨ ∧ ∧

Set if two’s complement overflow resulted from the operation; cleared otherwise.

NR7

Set if MSB of the result is set; cleared otherwise.

ZR7 R6 R5 R4 R3 R2 R1 R0 Z∧∧∧∧∧∧∧∧

The previous value remains unchanged when the result is zero; cleared otherwise.

CRd7 Rr7 Rr7 R7 R7 Rd7∧ ∨ ∧ ∨ ∧

Set if the absolute value of the contents of Rr plus previous carry is larger than the absolute value of the Rd;

cleared otherwise.

R (Result) equals Rd after the operation.

Example:

; Subtract r1:r0 from r3:r2

sub r2,r0 ; Subtract low byte

sbc r3,r1 ; Subtract with carry high byte

Words 1 (2 bytes)

Table 6-93. Cycles

Name Cycles

AVRe 1

AVRxm 1

AVRxt 1

AVRrc 1

6.94 SBCI – Subtract Immediate with Carry SBI – Set Bit in I/O Register

6.94.1 Description

Subtracts a constant from a register and subtracts with the C flag, and places the result in the destination register Rd.

Operation:

(i) Rd ← Rd - K - C

Syntax: Operands: Program Counter:

(i) SBCI Rd,K 16 ≤ d ≤ 31, 0 ≤ K ≤ 255 PC ← PC + 1

AVR® Instruction Set Manual

Instruction Description

16-bit Opcode:

0100 KKKK dddd KKKK

6.94.2 Status Register (SREG) and Boolean Formula

I T H S V N Z C

– – ⇔⇔⇔⇔⇔⇔

HRd3 K3 K3 R3 R3 Rd3∧ ∨ ∧ ∨ ∧

Set if there was a borrow from bit 3; cleared otherwise.

SN V, for signed tests.⊕

VRd7 K7 R7 Rd7 K7 R7∧ ∧ ∨ ∧ ∧

Set if two’s complement overflow resulted from the operation; cleared otherwise.

NR7

Set if MSB of the result is set; cleared otherwise.

ZR7 R6 R5 R4 R3 R2 R1 R0 Z∧∧∧∧∧∧∧∧

The previous value remains unchanged when the result is zero; cleared otherwise.

CRd7 K7 K7 R7 R7 Rd7∧ ∨ ∧ ∨ ∧

Set if the absolute value of the constant plus previous carry is larger than the absolute value of Rd; cleared

otherwise.

R (Result) equals Rd after the operation.

Example:

; Subtract 0x4F23 from r17:r16

subi r16,0x23 ; Subtract low byte

sbci r17,0x4F ; Subtract with carry high byte

Words 1 (2 bytes)

Table 6-94. Cycles

Name Cycles

AVRe 1

AVRxm 1

AVRxt 1

AVRrc 1

6.95 SBI – Set Bit in I/O Register

6.95.1 Description

Sets a specified bit in an I/O Register. This instruction operates on the lower 32 I/O Registers – addresses 0-31.

Operation:

AVR® Instruction Set Manual

Instruction Description

(i) I/O(A,b) ← 1

Syntax: Operands: Program Counter:

(i) SBI A,b 0 ≤ A ≤ 31, 0 ≤ b ≤ 7 PC ← PC + 1

16-bit Opcode:

1001 1010 AAAA Abbb

6.95.2 Status Register (SREG) and Boolean Formula

I T H S V N Z C

– – – – – – – –

Example:

sbi 0x1C,0 ; Set bit 0 at address 0x1C

Words 1 (2 bytes)

Table 6-95. Cycles

Name Cycles

AVRe 2

AVRxm 1

AVRxt 1

AVRrc 1

6.96 SBIC – Skip if Bit in I/O Register is Cleared

6.96.1 Description

This instruction tests a single bit in an I/O Register and skips the next instruction if the bit is cleared. This instruction

operates on the lower 32 I/O Registers – addresses 0-31.

Operation:

(i) If I/O(A,b) == 0 then PC ← PC + 2 (or 3) else PC ← PC + 1

Syntax: Operands: Program Counter:

(i) SBIC A,b 0 ≤ A ≤ 31, 0 ≤ b ≤ 7 PC ← PC + 1, Condition false - no

skip

PC ← PC + 2, Skip a one word

instruction

PC ← PC + 3, Skip a two word

instruction

16-bit Opcode:

1001 1001 AAAA Abbb

AVR® Instruction Set Manual

Instruction Description

6.96.2 Status Register (SREG) and Boolean Formula

I T H S V N Z C

– – – – – – – –

Example:

wait:

sbic 0x1C,1 ; Skip next instruction if 0x1C bit 1 is cleared

rjmp wait ; Bit not cleared yet

nop ; Continue (do nothing)

Words 1 (2 bytes)

Table 6-96. Cycles

Name Cycles

i ii iii

AVRe 1 2 3

AVRxm 2 3 4

AVRxt 1 2 3

AVRrc 1 2 N/A

i) If the condition is false (no skip).

ii) If the condition is true (skip is executed) and the instruction skipped is one word.

iii) If the condition is true (skip is executed) and the instruction skipped is two words.

6.97 SBIS – Skip if Bit in I/O Register is Set

6.97.1 Description

This instruction tests a single bit in an I/O Register and skips the next instruction if the bit is set. This instruction

operates on the lower 32 I/O Registers – addresses 0-31.

Operation:

(i) If I/O(A,b) == 1 then PC ← PC + 2 (or 3) else PC ← PC + 1

Syntax: Operands: Program Counter:

(i) SBIS A,b 0 ≤ A ≤ 31, 0 ≤ b ≤ 7 PC ← PC + 1, Condition false - no

skip

PC ← PC + 2, Skip a one word

instruction

PC ← PC + 3, Skip a two word

instruction

16-bit Opcode:

1001 1011 AAAA Abbb

AVR® Instruction Set Manual

Instruction Description

6.97.2 Status Register (SREG) and Boolean Formula

I T H S V N Z C

– – – – – – – –

Example:

waitset:

sbis 0x10,0 ; Skip next instruction if bit 0 at 0x10 is set

rjmp waitset ; Bit not set

nop ; Continue (do nothing)

Words 1 (2 bytes)

Table 6-97. Cycles

Name Cycles

i ii iii

AVRe 1 2 3

AVRxm 2 3 4

AVRxt 1 2 3

AVRrc 1 2 N/A

i) If the condition is false (no skip).

ii) If the condition is true (skip is executed) and the instruction skipped is one word.

iii) If the condition is true (skip is executed) and the instruction skipped is two words.

6.98 SBIW – Subtract Immediate from Word

6.98.1 Description

Subtracts an immediate value (0-63) from a register pair and places the result in the register pair. This instruction

operates on the upper four register pairs and is well suited for operations on the Pointer Registers.

This instruction is not available on all devices. Refer to .Appendix A

Operation:

(i) R[d+1]:Rd ← R[d+1]:Rd - K

Syntax: Operands: Program Counter:

(i) SBIW Rd,K d {24,26,28,30}, 0 ≤ K ≤ 63 PC ← PC + 1∈

16-bit Opcode:

1001 0111 KKdd KKKK

6.98.2 Status Register (SREG) and Boolean Formula

I T H S V N Z C

–––⇔⇔⇔⇔⇔

AVR® Instruction Set Manual

Instruction Description

SN V, for signed tests.⊕

VR15 Rdh7∧

Set if two’s complement overflow resulted from the operation; cleared otherwise.

NR15

Set if MSB of the result is set; cleared otherwise.

ZR15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0∧ ∧ ∧ ∧ ∧ ∧ ∧ ∧ ∧ ∧ ∧ ∧ ∧ ∧ ∧

Set if the result is ; cleared otherwise.0x0000

CR15 Rdh7∧

Set if the absolute value of K is larger than the absolute value of Rd; cleared otherwise.

R (Result) equals R[d+1]:Rd after the operation.

Example:

sbiw r24,1 ; Subtract 1 from r25:r24

sbiw YL,63 ; Subtract 63 from the Y-pointer(r29:r28)

Words 1 (2 bytes)

Table 6-98. Cycles

Name Cycles

AVRe 2

AVRxm 2

AVRxt 2

AVRrc N/A

6.99 SBR – Set Bits in Register

6.99.1 Description

Sets specified bits in register Rd. Performs the logical ORI between the contents of register Rd and a constant mask

K, and places the result in the destination register Rd. (Equivalent to ORI Rd,K.)

Operation:

(i) Rd ← Rd v K

Syntax: Operands: Program Counter:

(i) SBR Rd,K 16 ≤ d ≤ 31, 0 ≤ K ≤ 255 PC ← PC + 1

16-bit Opcode:

0110 KKKK dddd KKKK

6.99.2 Status Register (SREG) and Boolean Formula

I T H S V N Z C

– – – 0 –⇔ ⇔ ⇔

AVR® Instruction Set Manual

Instruction Description

SN V, for signed tests.⊕

Cleared.

NR7

Set if MSB of the result is set; cleared otherwise.

ZR7 R6 R5 R4 R3 R2 R1 R0∧∧∧∧∧∧∧

Set if the result is ; cleared otherwise.0x00

R (Result) equals Rd after the operation.

Example:

sbr r16,3 ; Set bits 0 and 1 in r16

sbr r17,0xF0 ; Set 4 MSB in r17

Words 1 (2 bytes)

Table 6-99. Cycles

Name Cycles

AVRe 1

AVRxm 1

AVRxt 1

AVRrc 1

6.100 SBRC – Skip if Bit in Register is Cleared

6.100.1 Description

This instruction tests a single bit in a register and skips the next instruction if the bit is cleared.

Operation:

(i) If Rr(b) == 0 then PC ← PC + 2 (or 3) else PC ← PC + 1

Syntax: Operands: Program Counter:

(i) SBRC Rr,b 0 ≤ r ≤ 31, 0 ≤ b ≤ 7 PC ← PC + 1, Condition false - no

skip

PC ← PC + 2, Skip a one word

instruction

PC ← PC + 3, Skip a two word

instruction

16-bit Opcode:

1111 110r rrrr 0bbb

AVR® Instruction Set Manual

Instruction Description

6.100.2 Status Register (SREG) and Boolean Formula

I T H S V N Z C

– – – – – – – –

Example:

sub r0,r1 ; Subtract r1 from r0

sbrc r0,7 ; Skip if bit 7 in r0 cleared

sub r0,r1 ; Only executed if bit 7 in r0 not cleared

nop ; Continue (do nothing)

Words 1 (2 bytes)

Table 6-100. Cycles

Name Cycles

i ii iii

AVRe 1 2 3

AVRxm 1 2 3

AVRxt 1 2 3

AVRrc 1 2 N/A

i) If the condition is false (no skip).

ii) If the condition is true (skip is executed) and the instruction skipped is one word.

iii) If the condition is true (skip is executed) and the instruction skipped is two words.

6.101 SBRS – Skip if Bit in Register is Set

6.101.1 Description

This instruction tests a single bit in a register and skips the next instruction if the bit is set.

Operation:

(i) If Rr(b) == 1 then PC ← PC + 2 (or 3) else PC ← PC + 1

Syntax: Operands: Program Counter:

(i) SBRS Rr,b 0 ≤ r ≤ 31, 0 ≤ b ≤ 7 PC ← PC + 1, Condition false - no

skip

PC ← PC + 2, Skip a one word

instruction

PC ← PC + 3, Skip a two word

instruction

16-bit Opcode:

1111 111r rrrr 0bbb

AVR® Instruction Set Manual

Instruction Description

6.101.2 Status Register (SREG) and Boolean Formula

I T H S V N Z C

– – – – – – – –

Example:

sub r0,r1 ; Subtract r1 from r0

sbrs r0,7 ; Skip if bit 7 in r0 set

neg r0 ; Only executed if bit 7 in r0 not set

nop ; Continue (do nothing)

Words 1 (2 bytes)

Table 6-101. Cycles

Name Cycles

i ii iii

AVRe 1 2 3

AVRxm 1 2 3

AVRxt 1 2 3

AVRrc 1 2 N/A

i) If the condition is false (no skip).

ii) If the condition is true (skip is executed) and the instruction skipped is one word.

iii) If the condition is true (skip is executed) and the instruction skipped is two words.

6.102 SEC – Set Carry Flag

6.102.1 Description

Sets the Carry (C) flag in SREG (Status Register). (Equivalent to instruction BSET 0.)

Operation:

(i) C ← 1

Syntax: Operands: Program Counter:

(i) SEC None PC ← PC + 1

16-bit Opcode:

1001 0100 0000 1000

6.102.2 Status Register (SREG) and Boolean Formula

I T H S V N Z C

– – – – – – – 1

AVR® Instruction Set Manual

Instruction Description

Carry flag set.

Example:

sec ; Set Carry flag

adc r0,r1 ; r0=r0+r1+1

Words 1 (2 bytes)

Table 6-102. Cycles

Name Cycles

AVRe 1

AVRxm 1

AVRxt 1

AVRrc 1

6.103 SEH – Set Half Carry Flag

6.103.1 Description

Sets the Half Carry (H) flag in SREG (Status Register). (Equivalent to instruction BSET 5.)

Operation:

(i) H ← 1

Syntax: Operands: Program Counter:

(i) SEH None PC ← PC + 1

16-bit Opcode:

1001 0100 0101 1000

6.103.2 Status Register (SREG) and Boolean Formula

I T H S V N Z C

– – 1 – – – – –

Half Carry flag set.

Example:

seh ; Set Half Carry flag

Words 1 (2 bytes)

Table 6-103. Cycles

Name Cycles

AVRe 1

AVR® Instruction Set Manual

Instruction Description

...........continued

Name Cycles

AVRxm 1

AVRxt 1

AVRrc 1

6.104 SEI – Set Global Interrupt Enable Bit

6.104.1 Description

Sets the Global Interrupt Enable (I) bit in SREG (Status Register). The instruction following SEI will be executed

before any pending interrupts.

Operation:

(i) I ← 1

Syntax: Operands: Program Counter:

(i) SEI None PC ← PC + 1

16-bit Opcode:

1001 0100 0111 1000

6.104.2 Status Register (SREG) and Boolean Formula

I T H S V N Z C

1 – – – – – – –

Global Interrupt Enable bit set.

Example:

sei ; set global interrupt enable

sleep ; enter sleep, waiting for interrupt

; note: will enter sleep before any pending interrupt(s)

Words 1 (2 bytes)

Table 6-104. Cycles

Name Cycles

AVRe 1

AVRxm 1

AVRxt 1

AVRrc 1

AVR® Instruction Set Manual

Instruction Description

6.105 SEN – Set Negative Flag

6.105.1 Description

Sets the Negative (N) flag in SREG (Status Register). (Equivalent to instruction BSET 2.)

Operation:

(i) N ← 1

Syntax: Operands: Program Counter:

(i) SEN None PC ← PC + 1

16-bit Opcode:

1001 0100 0010 1000

6.105.2 Status Register (SREG) and Boolean Formula

I T H S V N Z C

– – – – – 1 – –

Negative flag set.

Example:

add r2,r19 ; Add r19 to r2

sen ; Set Negative flag

Words 1 (2 bytes)

Table 6-105. Cycles

Name Cycles

AVRe 1

AVRxm 1

AVRxt 1

AVRrc 1

6.106 SER – Set all Bits in Register

6.106.1 Description

Loads directly to register Rd. (Equivalent to instruction LDI Rd,0xFF).0xFF

Operation:

(i) Rd ← 0xFF

Syntax: Operands: Program Counter:

AVR® Instruction Set Manual

Instruction Description

Sign flag set.

Example:

add r2,r19 ; Add r19 to r2

ses ; Set Negative flag

Words 1 (2 bytes)

Table 6-107. Cycles

Name Cycles

AVRe 1

AVRxm 1

AVRxt 1

AVRrc 1

6.108 SET – Set T Bit

6.108.1 Description

Sets the T bit in SREG (Status Register). (Equivalent to instruction BSET 6.)

Operation:

(i) T ← 1

Syntax: Operands: Program Counter:

(i) SET None PC ← PC + 1

16-bit Opcode:

1001 0100 0110 1000

6.108.2 Status Register (SREG) and Boolean Formula

I T H S V N Z C

– 1 – – – – – –

T bit set.

Example:

set ; Set T bit

Words 1 (2 bytes)

Table 6-108. Cycles

Name Cycles

AVRe 1

AVR® Instruction Set Manual

Instruction Description

Produktspecifikationer

Varumärke:	Microchip
Kategori:	Inte kategoriserad
Modell:	AVR128DA32

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