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HRPWM with Fine Edge

Placement

dsPIC33/PIC24 Family Reference Manual

Introduction

Note: This family reference manual section is meant to serve as a complement to device data sheets. Depending on

the device variant, this manual section may not apply to all dsPIC33 devices. Please consult the note at the

beginning of the chapter in the specific device data sheet to check whether this document supports the device you

are using.

Device data sheets and family reference manual sections are available for download from the Microchip Worldwide

Website at: www.microchip.com.

This document describes the features and use of the High-Resolution Pulse-Width Modulated (PWM) with Fine Edge

Placement. This flexible module provides features to support many types of Motor Control (MC) and Power Control

(PC) applications, including:

• AC-to-DC Converters

• DC-to-DC Converters

• AC and DC Motor Control: Brushed DC, BLDC, PMSM, ACIM, SRM, Stepper, etc.

• Inverters

• Battery Chargers

• Digital Lighting

• Power Factor Correction (PFC)

High-Level Features

• Up to Eight Independent PWM Generators, each with Dual Outputs

• Operating modes:

– Independent Edge PWM mode

– Variable Phase PWM mode

– Independent Edge PWM mode, Dual Output

– Center-Aligned PWM mode

– Double Update Center-Aligned PWM mode

– Dual Edge Center-Aligned PWM mode

• Output modes:

– Complementary

– Independent

– Push-Pull

• Dead-Time Generator

• Dead-Time Compensation

• Leading-Edge Blanking (LEB)

• Output Override for Fault Handling

• Flexible Period/Duty Cycle Updating Options

• PWM Control Inputs (PCI) for PWM Pin Overrides and External PWM Synchronization

• Advanced Triggering Options

• Combinatorial Logic Output

• PWM Event Outputs

HRPWM with Fine Edge Placement

Table of Contents

Introduction.....................................................................................................................................................1

High-Level Features....................................................................................................................................... 1

1. Registers................................................................................................................................................. 5

2. Register Maps......................................................................................................................................... 6

2.1. Common Functions Register Map................................................................................................7

2.2. PWM Generator Register Map................................................................................................... 21

3. Architecture Overview...........................................................................................................................51

4. Operation.............................................................................................................................................. 54

4.1. PWM Clocking............................................................................................................................54

4.2. PWM Generator (PG) Features..................................................................................................59

4.3. Common Features......................................................................................................................95

4.4. Lock and Write Restrictions......................................................................................................100

5. Application Examples..........................................................................................................................105

5.1. Six-Step Commutation of Three-Phase BLDC Motor...............................................................105

5.2. Three-Phase Sinusoidal Control of PMSM/ACIM Motors.........................................................114

5.3. Simple Complementary PWM Output.......................................................................................117

5.4. Cycle-by-Cycle Current Limit Mode..........................................................................................118

5.5. External Period Reset Mode.................................................................................................... 120

6. Interrupts............................................................................................................................................. 123

7. Operation in Power-Saving Modes..................................................................................................... 124

7.1. Operation in Sleep Mode..........................................................................................................124

7.2. Operation in Idle Mode............................................................................................................. 124

8. Related Application Notes...................................................................................................................125

9. Revision History.................................................................................................................................. 126

9.1. Revision A (August 2017).........................................................................................................126

9.2. Revision B (February 2018)..................................................................................................... 126

9.3. Revision C (February 2019)..................................................................................................... 126

9.4. Revision D (December 2020)................................................................................................... 126

The Microchip Website...............................................................................................................................128

Product Change Notification Service..........................................................................................................128

Customer Support...................................................................................................................................... 128

Microchip Devices Code Protection Feature..............................................................................................128

Legal Notice............................................................................................................................................... 129

Trademarks................................................................................................................................................ 129

Quality Management System..................................................................................................................... 130

HRPWM with Fine Edge Placement

Worldwide Sales and Service.....................................................................................................................131

HRPWM with Fine Edge Placement

1. Registers

There are two categories of Special Function Registers (SFRs) used to control the operation of the PWM module:

• Common, shared by all PWM Generators

• PWM Generator-specific

An ‘x’ in the register name denotes an instance of a PWM Generator.

A ‘y’ in the register name denotes an instance of a common function.

The LOCK bit in the PCLKCON register may be set in software to block writes to certain registers and bits. See 4.2

PWM Generator (PG) Features for more information. Writes to certain data and control registers are not safe at

certain times of a PWM cycle or when the module is enabled.

HRPWM with Fine Edge Placement

Registers

2.1 Common Functions Register Map

Note: The number of LOGCONy and PWMEVTy registers are device-dependent. Refer to the device data sheet for

availability.

Name Bit Pos. 7 6 5 4 3 2 1 0

PCLKCON 7:0 DIVSEL[1:0] MCLKSEL[1:0]

15:8 HRRDY HRERR LOCK

FSCL 7:0 FSCL[7:0]

15:8 FSCL[15:8]

FSMINPER 7:0 FSMINPER[7:0]

15:8 FSMINPER[15:8]

MPHASE 7:0 MPHASE[7:0]

15:8 MPHASE[15:8]

MDC 7:0 MDC[7:0]

15:8 MDC[15:8]

MPER 7:0 MPER[7:0]

15:8 MPER[15:8]

LFSR 7:0 LFSR[7:0]

15:8 LFSR[14:8]

CMBTRIGL 7:0 CTA8EN CTA7EN CTA6EN CTA5EN CTA4EN CTA3EN CTA2EN CTA1EN

15:8

CMBTRIGH 7:0 CTB8EN CTB7EN CTB6EN CTB5EN CTB4EN CTB3EN CTB2EN CTB1EN

15:8

LOGCONy 7:0 S1yPOL S2yPOL PWMLFy[1:0] PWMLFyD[2:0]

15:8 PWMS1y[3:0] PWMS2y[3:0]

PWMEVTy 7:0 EVTySEL[3:0] EVTyPGS[2:0]

15:8 EVTyOEN EVTyPOL EVTySTRD EVTySYNC

HRPWM with Fine Edge Placement

2.1.3 Frequency Scaling Minimum Period Register

Name: FSMINPER

Bit 15 14 13 12 11 10 9 8

FSMINPER[15:8]

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bit 7 6 5 4 3 2 1 0

FSMINPER[7:0]

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bits 15:0 – FSMINPER[15:0] Frequency Scaling Minimum Period Register

This register holds the minimum clock period (maximum clock frequency) that can be produced by the frequency

scaling circuit.

HRPWM with Fine Edge Placement

2.1.5 Master Duty Cycle Register

Name: MDC

Bit 15 14 13 12 11 10 9 8

MDC[15:8]

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bit 7 6 5 4 3 2 1 0

MDC[7:0]

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bits 15:0 – MDC[15:0] Master Duty Cycle Register

This register holds the duty cycle value that can be shared by multiple PWM Generators.

Note: Duty cycle values less than 0x0008 should not be used (0x0020 in High-Resolution mode).

HRPWM with Fine Edge Placement

2.1.6 Master Period Register

Name: MPER

Bit 15 14 13 12 11 10 9 8

MPER[15:8]

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bit 7 6 5 4 3 2 1 0

MPER[7:0]

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bits 15:0 – MPER[15:0] Master Period Register

This register holds the period value that can be shared by multiple PWM Generators.

Note: Period values less than 0x0020 should not be used (0x0080 in High-Resolution mode).

HRPWM with Fine Edge Placement

2.1.11 PWM Event Output Control Register y

Name: PWMEVTy

Note: ‘y’ denotes a common instance (A-F); the number of the available combinatorial PWM logic is

device-dependent. Refer to the device data sheet for availability.

Bit 15 14 13 12 11 10 9 8

EVTyOEN EVTyPOL EVTySTRD EVTySYNC

Access R/W R/W R/W R/W

Reset 0 0 0 0

Bit 7 6 5 4 3 2 1 0

EVTySEL[3:0] EVTyPGS[2:0]

Access R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0

Bit 15 – EVTyOEN PWM Event Output Enable

Value Description

1Event output signal is output on the PWMEy pin

0Event output signal is internal only

Bit 14 – EVTyPOL PWM Event Output Polarity

Value Description

1Event output signal is active-low

0Event output signal is active-high

Bit 13 – EVTySTRD PWM Event Output Stretch Disable

Note: The event signal is stretched using peripheral_clk because different PWM Generators may be operating from

different clock sources.

Value Description

1Event output signal pulse width is not stretched

0Event output signal is stretched to eight PWM clock cycles minimum

Bit 12 – EVTySYNC PWM Event Output Sync

Event output signal pulse will be synchronized to peripheral_clk.

Value Description

1Event output signal is synchronized to the system clock

0Event output is not synchronized to the system clock

Bits 7:4 – EVTySEL[3:0] PWM Event Selection

Note: This is the PWM Generator output signal prior to Output mode logic and any output override logic.

Value Description

1111 High-resolution error event signal

1110-1010 Reserved

1001 ADC Trigger 2 signal

1000 ADC Trigger 1 signal

0111 STEER signal (available in Push-Pull Output modes only)

0110 CAHALF signal (available in Center-Aligned modes only)

0101 PCI Fault active output signal

0100 PCI current limit active output signal

0011 PCI feed-forward active output signal

0010 PCI Sync active output signal

0001 PWM Generator output signal

(1)

0000 Source is selected by the [2:0] bitsPGTRGSEL

HRPWM with Fine Edge Placement

2.2.1 PWM Generator x Control Register Low

Name: PGxCONL

Bit 15 14 13 12 11 10 9 8

ON TRGCNT[2:0]

Access R/W R/W R/W R/W

Reset 0 0 0 0

Bit 7 6 5 4 3 2 1 0

HREN CLKSEL[1:0] MODSEL[2:0]

Access R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0

Bit 15 – ON PWM Generator x Enable

Value Description

1PWM Generator is enabled

0PWM Generator is not enabled

Bits 10:8 – TRGCNT[2:0] PWM Generator x Trigger Count Select

Value Description

111 PWM Generator produces 8 PWM cycles after triggered

110 PWM Generator produces 7 PWM cycles after triggered

101 PWM Generator produces 6 PWM cycles after triggered

100 PWM Generator produces 5 PWM cycles after triggered

011 PWM Generator produces 4 PWM cycles after triggered

010 PWM Generator produces 3 PWM cycles after triggered

001 PWM Generator produces 2 PWM cycles after triggered

000 PWM Generator produces 1 PWM cycle after triggered

Bit 7 – HREN PWM Generator x High-Resolution Enable

Note: This bit is not present on all devices. Refer to the device-specific data sheet for availability. When High-

Resolution mode is not available, this bit will read as ‘ ’.0

Value Description

1PWM Generator x operates in High-Resolution mode

0PWM Generator x operates in Standard Resolution mode

Bits 4:3 – CLKSEL[1:0] Clock Selection(1)

Notes:

1. Do not change the CLKSEL[1:0] bits while ON (PGxCONL[15]) = .1

2. The PWM Generator time base operates from the frequency scaling circuit clock, effectively scaling the duty

cycle and period of the PWM Generator output.

3. This clock source should not be used when HREN (PGxCONL[7]) = .1

Value Description

11 PWM Generator uses the master clock scaled by the frequency scaling circuit

(2,3)

10 PWM Generator uses the master clock divided by the clock divider circuit

(2)

01 PWM Generator uses the master clock selected by the MCLKSEL[1:0] (PCLKCON[1:0]) control bits

00 No clock selected, PWM Generator is in the lowest power state (default)

Bits 2:0 – MODSEL[2:0] PWM Generator x Mode Selection

Value Description

111 Dual Edge Center-Aligned PWM mode (interrupt/register update twice per cycle)

110 Dual Edge Center-Aligned PWM mode (interrupt/register update once per cycle)

101 Double Update Center-Aligned PWM mode

HRPWM with Fine Edge Placement

Produktspecifikationer

Varumärke:	Microchip
Kategori:	Inte kategoriserad
Modell:	dsPIC33CK256MPT608

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