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2007-2020 Microchip Technology Inc. DS70000185D-page 1
HIGHLIGHTS
This section of the manual contains the following major topics:
1.0 Introduction ....................................................................................................................... 2
2.0 CAN Message Formats..................................................................................................... 4
3.0 Register Maps................................................................................................................... 8
4.0 CAN Registers ................................................................................................................ 15
5.0 CAN Message Buffers .................................................................................................... 34
6.0 Bit Timing ........................................................................................................................ 38
7.0 CAN Operating Modes.................................................................................................... 42
8.0 Transmitting CAN Messages .......................................................................................... 43
9.0 Receiving CAN Messages .............................................................................................. 50
10.0 DMA Controller Configuration ......................................................................................... 63
11.0 CAN Error Management ................................................................................................. 66
12.0 CAN Interrupts ................................................................................................................ 69
13.0 CAN Low-Power Modes.................................................................................................. 72
14.0 CAN Time Stamping Using Input Capture ...................................................................... 72
15.0 Related Application Notes............................................................................................... 73
16.0 Revision History .............................................................................................................. 74
Enhanced Controller Area Network (CAN)
dsPIC33F/PIC24H Family Reference Manual
DS70000185D-page 2 2007-2020 Microchip Technology Inc.
1.0 INTRODUCTION
The dsPIC33F/PIC24H Enhanced Controller Area Network (CAN) module implements the CAN
Protocol 2.0B, used primarily in industrial and automotive applications. This asynchronous serial
data communication protocol provides reliable communications in electrically noisy environ-
ments. The dsPIC33F device family integrates up to two CAN modules. Figure 1-1 illustrates a
typical CAN bus topology.
Figure 1-1: Typical CAN Bus Network
The CAN module supports the following key features:
Standards Compliance:
• Full CAN 2.0B compliance
• Programmable bit rate up to 1 Mbps
Message Reception:
• 32 message buffers – all of them can be used for reception
• 16 acceptance filters for message filtering
• Three acceptance filter mask registers for message filtering
• Automatic response to Remote Transmit Request
• Up to 32-message deep First-In First-Out (FIFO) buffer
• DeviceNet™ addressing support
• DMA interface for message reception
Note: This family reference manual section is meant to serve as a complement to device
data sheets. Depending on the device variant, this manual section may not apply to
all dsPIC33/PIC24 devices.
Please consult the note at the beginning of the “Direct Memory Access (DMA)”
chapter in the current device data sheet to check whether this document supports
the device you are using.
Device data sheets and family reference manual sections are available for
download from the Microchip Worldwide Website at: http://www.microchip.com
CAN
bus
CAN1
PIC® MCU
with Integrated
CAN
CAN
Transceiver
dsPIC33F/PIC24H
with Integrated
CAN™
dsPIC33/PIC24
with Integrated
CAN
Transceiver
CAN Transceiver
CAN
Transceiver
CAN
CAN2
CAN
Transceiver
dsPIC33F/PIC24H
2007-2020 Microchip Technology Inc. DS70000185D-page 3
Enhanced CAN Module
Message Transmission:
• Eight message buffers configurable for message transmission
• User-defined priority levels for message buffers used for transmission
• DMA interface for message transmission
Others:
• Loopback, Listen All Messages and Listen Only modes for self-test, system diagnostics
and bus monitoring
• Low-power operating modes
Figure 1-2 illustrates the general structure of the CAN module and its interaction with the DMA
Controller and DMA RAM.
Figure 1-2: CAN Interaction with DMA
1.1 CAN Module
The CAN module consists of a protocol engine, message acceptance filters, and separate trans-
mit and receive DMA interfaces. The protocol engine transmits and receives messages to and
from the CAN bus (as per CAN bus 2.0B protocol). The user-configurable acceptance filters are
used by the module to examine the received message to determine if it should be stored in the
DMA message buffer or discarded.
For received messages, the receive DMA interface generates a receive data interrupt to initiate
a DMA cycle. The receive DMA channel reads data from the CxRXD register and writes them
into the message buffer.
For transmit messages, the transmit DMA interface generates a transmit data interrupt to start a
DMA cycle. The transmit DMA channel reads from the message buffer and writes to the CxTXD
register for message transmission.
1.2 Message Buffers
The CAN module supports up to 32 message buffers for storing data transmitted or received on
the CAN bus. These buffers are located in DMA RAM. Message Buffers 0-7 can be configured
for either transmit or receive operation. Message Buffers 8-31 are receive-only buffers and
cannot be used for message transmission.
1.3 DMA Controller
The DMA controller acts as an interface between the message buffers and CAN to transfer data
back and forth without CPU intervention. The DMA controller supports up to eight channels for
transferring data between DMA RAM and the dsPIC33F peripherals. Two separate DMA
channels are needed to support CAN message transmission and CAN message reception.
Each DMA channel has a DMA Request (DMAxREQ) register, which is used by the user
application to assign an interrupt event to trigger a DMA-based message transfer.
CxTX
CxRX
Message Buffer 0
Message Buffer 7
Message Buffer 8
Message Buffer 31
CAN
Protocol
Engine
CAN
Transmit
Register
(CxTXD)
Acceptance
Filter 0-15
CAN
Receive
Register
(CxRXD)
TX DMA
Interface
RX DMA
Interface
DMA
Channel
DMA
Channel
Message Buffer 1
CAN Module Message Buffer
(DMA RAM)
RX
Request
TX
Request
dsPIC33F/PIC24H Family Reference Manual
DS70000185D-page 4 2007-2020 Microchip Technology Inc.
2.0 CAN MESSAGE FORMATS
The CAN bus protocol uses asynchronous communication. Information is passed from transmit-
ters to receivers in data frames, which are composed of byte fields that define the contents of the
data frame, as shown in Figure 2-1.
Each frame begins with a Start-of-Frame (SOF) bit and terminates with an End-of-Frame (EOF)
bit field. The Start-of-Frame is followed by Arbitration and Control fields, which identify the
message type, format, length and priority. This information allows each node on the CAN bus to
respond appropriately to the message. The Data field conveys the message content and is vari-
able length, ranging from 0 to 8 bytes. Error protection is provided by the Cyclic Redundancy
Check (CRC) and Acknowledgement (ACK) fields.
Figure 2-1: CAN Bus Message Frame
The CAN bus protocol supports five frame types:
•Data Frame – carries data from transmitter to the receivers
•Remote Frame – transmitted by a node on the bus, to request transmission of a data
frame with the same identifier from another node
•Error Frame – transmitted by any node when it detects an error
•Overload Frame – provides an extra delay between successive data or remote frames
•Interframe Space – provides a separation between successive frames
The CAN 2.0B specification defines two additional data formats:
•Standard Data Frame – intended for standard messages that use 11 identifier bits
•Extended Data Frame – intended for extended messages that use 29 identifier bits
There are three versions of CAN bus specifications:
•2.0A – considers a 29-bit identifier as an error
• 2.0B Passive – ignores 29-bit identifier messages
•2.0B Active – handles both 11-bit and 29-bit identifiers
The dsPIC33F CAN module is compliant with the CAN 2.0B active specification, while providing
enhanced message filtering capabilities.
Note: Refer to the Bosch CAN bus specification for detailed information on the CAN
protocol.
S
O
F
ARBITRATION CONTROL DATA E
O
F
ACKCRC
2007-2020 Microchip Technology Inc. DS70000185D-page 5
Enhanced CAN Module
2.1 Standard Data Frame
The standard data frame message begins with a Start-of-Frame bit followed by a 12-bit Arbitra-
tion field, as shown in Figure 2-2. The Arbitration field contains an 11-bit identifier and the
Remote Transmit Request (RTR) bit. The identifier defines the type of information contained in
the message and is used by each receiving node to determine if the message is of interest to it.
The RTR bit distinguishes a data frame from a remote frame. For a standard data frame, the RTR
bit is clear.
Following the Arbitration field is a 6-bit Control field, which provides more information about the
contents of the message. The first bit in the Control field is an Identifier Extension (IDE) bit, which
distinguishes the message as either a standard or extended data frame. A standard data frame
is indicated by a dominant state (logic level ‘0’) during transmission of the IDE bit. The second
bit in the Control field is a Reserved (RB0) bit, which is in the Dominant state (logic level ‘0’). The
last four bits in the Control field represent the Data Length Code (DLC), which specifies the
number of data bytes present in the message.
The Data field follows the Control field. This field carries the message data – the actual payload
of the data frame. This field is variable length, ranging from 0 to 8 bytes. The number of bytes is
user-selectable.
The Data field is followed by the Cyclic Redundancy Check field, which is a 15-bit CRC sequence
with one delimiter bit.
The Acknowledgement (ACK) field is sent as a recessive bit (logic level ‘1’) and is overwritten as
a dominant bit by any receiver that has received the data correctly. The message is
Acknowledged by the receiver, irrespective of the result of the acceptance filter comparison.
The last field is the End-of-Frame (EOF) field, which consists of seven recessive bits that indicate
the end of the message.
Figure 2-2: Format of the Standard Data Frame
SID10 SID1
S
O
F
IDENTIFIER
11 Bits
R
T
R
I
D
E
RB0 DLC
4 Bits
DATA
8 Bytes
CRC
16 Bits
ACK
2 Bits
EOF
7 Bits
IFS
3 Bits
SID0
11-Bit Identifier
Interframe Space
Data
Frame Interframe Space
IDE is Dominant (Logical ‘0’)
RTR is Dominant (Logical ‘0’)
RB0 is Dominant (Logical ‘0’)
Arbitration
Field
Control
Field
Field
CRC
Field
ACK
Field
End-of-
dsPIC33F/PIC24H Family Reference Manual
DS70000185D-page 6 2007-2020 Microchip Technology Inc.
2.2 Extended Data Frame
The extended data frame begins with a SOF bit, followed by a 31-bit Arbitration field, as shown
in Figure 2-3. The Arbitration field for the extended data frame contains 29 identifier bits in two
fields separated by a Substitute Remote Request (SRR) bit and an IDE bit. SRR = 1 for extended
data frames. The IDE bit indicates the data frame type. For the extended data frame, IDE = 1.
The extended data frame Control field consists of seven bits. The first bit is the RTR. For the
extended data frame, RTR = 0. The next two bits, RB1 and RB0, are reserved bits that are in the
Dominant state (logic level ‘0’). The last four bits in the Control field are the Data Length Code,
which specifies the number of data bytes present in the message.
The remaining fields in an extended data frame are identical to a standard data frame.
Figure 2-3: Format of the Extended Data Frame
SID10 SID1
S
O
F
IDENTIFIER
11 Bits
S
R
R
I
D
E
R
T
R
DLC
4 Bits
CRC
16 Bits
ACK
2 Bits
EOF
7 Bits
IFS
3 Bits
SID0
Field
29-Bit Identifier
Control CRC
IDENTIFIER
18 Bits
EID17 EID1 EID0
R
B
1
R
B
0
IDE is Recessive (Logical ‘1’)
SRR is Recessive (Logical ‘1’)
RTR is Dominant (Logical ‘0’)
RB0 is Dominant (Logical ‘0’)
RB1 is Dominant (Logical ‘0’)
ACK End-of-
Frame
Data
DATA
8 Bytes
Arbitration
Field Field Field Field
2007-2020 Microchip Technology Inc. DS70000185D-page 7
Enhanced CAN Module
2.3 Remote Frame
A node expecting to receive data from another node can initiate transmission of the respective
data by the source node by sending a remote frame. A remote frame can be in standard format
(see Figure 2-4) or extended format (see Figure 2-5).
A remote frame is similar to a data frame, with the following exceptions:
• The RTR bit is recessive (RTR = 1)
• There is no Data field
• The value of the DLC bits is 0  DLC 8
Figure 2-4: Format of the Standard Remote Frame
Figure 2-5: Format of the Extended Remote Frame
SID10 SID1
S
O
F
IDENTIFIER
11 Bits
R
T
R
I
D
E
DLC
4 Bits
CRC
16 Bits
ACK
2 Bits
EOF
7 Bits
IFS
3 Bits
SID0
11-Bit Identifier
RB0
IDE is Dominant (Logical ‘0’)
RTR is Recessive (Logical ‘1’)
RB0 is Dominant (Logical ‘0’)
Arbitration Field Control Field CRC Field ACK Field End-of-Frame
SID10 SID0
S
O
F
IDENTIFIER
11 Bits
S
R
R
I
D
E
R
T
R
DLC
4 Bits
CRC
16 Bits
ACK
2 Bits
EOF
7 Bits
IFS
3 Bits
SID1
Arbitration Field
29-Bit Identifier
Control Field CRC Field
IDENTIFIER
18 Bits
EID17 EID1 EID0
R
B
1
R
B
0
IDE is Recessive (Logical ‘1’)
SRR is Recessive (Logical ‘1’)
RTR is Recessive (Logical ‘1’)
RB0 is Dominant (Logical ‘0’)
RB1 is Dominant (Logical ‘0’)
ACK Field
End-of-
Frame
2007-2020 Microchip Technology Inc. DS70000185D-page 9
Table 3-1: CAN1 Register Map When C1CTRL1.WIN = 0 or 1
File Name Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2
C1CTRL1 — — CSIDL ABAT — REQOP[2:0] OPMODE[2:0] — CANCAP —
C1CTRL2 — — — — — — — — — — — DNCNT[4
C1VEC — — — FILHIT[4:0] — ICODE[6:0]
C1FCTRL DMABS[2:0] — — — — — — — — FSA[4:0
C1FIFO — —— FBP[5:0] — FNRB[5:0]
C1INTF — — TXBO TXBP RXBP TXWAR RXWAR EWARN IVRIF WAKIF ERRIF — FIFOIF RBOV
C1INTE — — — — — — — — IVRIE WAKIE ERRIE — FIFOIE RBOV
C1EC TERRCNT[7:0] RERRCNT[7:0]
C1CFG1 — — — — — — — — SJW[1:0] BRP[5:0]
C1CFG2 — WAKFIL — — — SEG2PH[2:0] SEG2PHTS SAM SEG1PH[2:0]
C1FEN1
FLTEN[15:0]
C1FMSKSEL1
F7MSK[1:0] F6MSK[1:0] F5MSK[1:0] F4MSK[1:0] F3MSK[1:0] F2MSK[1:0] F1MSK[1:0]
C1FMSKSEL2
F15MSK[1:0] F14MSK[1:0] F13MSK[1:0] F12MSK[1:0] F11MSK[1:0] F10MSK[1:0] F9MSK[1:0]
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Table 3-2: CAN1 Register Map When C1CTRL1.WIN = 0
File Name Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2
See definition when WIN = x
C1RXFUL1
RXFUL[15:0]
C1RXFUL2
RXFUL[31:16]
C1RXOVF1
RXOVF[15:0]
C1RXOVF2
RXOVF[31:16]
C1TR01CON TXEN1 TXABT1 TXLARB1 TXERR1 TXREQ1 RTREN1 TX1PRI[1:0] TXEN0 TXABT0 TXLARB0 TXERR0 TXREQ0 RTREN
C1TR23CON TXEN3 TXABT3 TXLARB3 TXERR3 TXREQ3 RTREN3 TX3PRI[1:0] TXEN2 TXABT2 TXLARB2 TXERR2 TXREQ2 RTREN
C1TR45CON TXEN5 TXABT5 TXLARB5 TXERR5 TXREQ5 RTREN5 TX5PRI[1:0] TXEN4 TXABT4 TXLARB4 TXERR4 TXREQ4 RTREN
C1TR67CON TXEN7 TXABT7 TXLARB7 TXERR7 TXREQ7 RTREN7 TX7PRI[1:0] TXEN6 TXABT6 TXLARB6 TXERR6 TXREQ6 RTREN
C1RXD Receive Data Word
C1TXD Transmit Data Word
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
DS70000185D-page 10 2007-2020 Microchip Technology Inc.
Table 3-3: CAN1 Register Map When C1CTRL1.WIN = 1
File Name Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2
See definition when WIN = x
C1BUFPNT1 F3BP[3:0] F2BP[3:0] F1BP[3:0] F0B
C1BUFPNT2 F7BP[3:0] F6BP[3:0] F5BP[3:0] F4B
C1BUFPNT3 F11BP[3:0] F10BP[3:0] F9BP[3:0] F8B
C1BUFPNT4 F15BP[3:0] F14BP[3:0] F13BP[3:0] F12B
C1RXM0SID SID[10:3] SID[2:0] — MIDE —
C1RXM0EID EID[15:8] EID[7:0]
C1RXM1SID SID[10:3] SID[2:0] — MIDE —
C1RXM1EID EID[15:8] EID[7:0]
C1RXM2SID SID[10:3] SID[2:0] — MIDE —
C1RXM2EID EID[15:8] EID[7:0]
C1RXF0SID SID[10:3] SID[2:0] — EXIDE —
C1RXF0EID EID[15:8] EID[7:0]
C1RXF1SID SID[10:3] SID[2:0] — EXIDE —
C1RXF1EID EID[15:8] EID[7:0]
C1RXF2SID SID[10:3] SID[2:0] — EXIDE —
C1RXF2EID EID[15:8] EID[7:0]
C1RXF3SID SID[10:3] SID[2:0] — EXIDE —
C1RXF3EID EID[15:8] EID[7:0]
C1RXF4SID SID[10:3] SID[2:0] — EXIDE —
C1RXF4EID EID[15:8] EID[7:0]
C1RXF5SID SID[10:3] SID[2:0] — EXIDE —
C1RXF5EID EID[15:8] EID[7:0]
C1RXF6SID SID[10:3] SID[2:0] — EXIDE —
C1RXF6EID EID[15:8] EID[7:0]
C1RXF7SID SID[10:3] SID[2:0] — EXIDE —
C1RXF7EID EID[15:8] EID[7:0]
C1RXF8SID SID[10:3] SID[2:0] — EXIDE —
C1RXF8EID EID[15:8] EID[7:0]
C1RXF9SID SID[10:3] SID[2:0] — EXIDE —
C1RXF9EID EID[15:8] EID[7:0]
C1RXF10SID SID[10:3] SID[2:0] — EXIDE —
C1RXF10EID EID[15:8] EID[7:0]
C1RXF11SID SID[10:3] SID[2:0] — EXIDE —
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
2007-2020 Microchip Technology Inc. DS70000185D-page 11
C1RXF11EID EID[15:8] EID[7:0]
C1RXF12SID SID[10:3] SID[2:0] — EXIDE —
C1RXF12EID EID[15:8] EID[7:0]
C1RXF13SID SID[10:3] SID[2:0] — EXIDE —
C1RXF13EID EID[15:8] EID[7:0]
C1RXF14SID SID[10:3] SID[2:0] — EXIDE —
C1RXF14EID EID[15:8] EID[7:0]
C1RXF15SID SID[10:3] SID[2:0] — EXIDE —
C1RXF15EID EID[15:8] EID[7:0]
Table 3-3: CAN1 Register Map When C1CTRL1.WIN = 1 (Continued)
File Name Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
DS70000185D-page 12 2007-2020 Microchip Technology Inc.
Table 3-4: CAN2 Register Map When C2CTRL1.WIN = 0 or 1
File Name Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2
C2CTRL1 — — CSIDL ABAT — REQOP[2:0] OPMODE[2:0] —
CANCAP
—
C2CTRL2 — — — — — — — — — — — DNCNT[4
C2VEC — — — FILHIT[4:0] — ICODE[6:0]
C2FCTRL DMABS[2:0] — — — — — — — — FSA[4:0
C2FIFO — —— FBP[5:0] — FNRB[5:0]
C2INTF — — TXBO TXBP RXBP TXWAR RXWAR
EWARN
IVRIF WAKIF ERRIF — FIFOIF RBOVIF
C2INTE — — — — — — — — IVRIE WAKIE ERRIE — FIFOIE RBOVIE
C2EC TERRCNT[7:0] RERRCNT[7:0]
C2CFG1 — — — — — — — — SJW[1:0] BRP[5:0]
C2CFG2 — WAKFIL — — — SEG2PH[2:0]
SEG2PHTS
SAM SEG1PH[2:0]
C2FEN1 FLTEN[15:0]
C2FMSKSEL1
F7MSK[1:0] F6MSK[1:0] F5MSK[1:0] F4MSK[1:0] F3MSK[1:0] F2MSK[1:0] F1MSK[1:0]
C2FMSKSEL2
F15MSK[1:0] F14MSK[1:0] F13MSK[1:0] F12MSK[1:0] F11MSK[1:0] F10MSK[1:0] F9MSK[1:0]
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Table 3-5: CAN2 Register Map When C2CTRL1.WIN = 0
File Name Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2
See definition when WIN = x
C2RXFUL1
RXFUL[15:0]
C2RXFUL2
RXFUL[31:16]
C2RXOVF1
RXOVF[15:0]
C2RXOVF2
RXOVF[31:16]
C2TR01CON TXEN1 TXABAT1 TXLARB1 TXERR1 TXREQ1 RTREN1 TX1PRI[1:0] TXEN0 TXABAT0 TXLARB0 TXERR0 TXREQ0 RTREN0
C2TR23CON TXEN3 TXABAT3 TXLARB3 TXERR3 TXREQ3 RTREN3 TX3PRI[1:0] TXEN2 TXABAT2 TXLARB2 TXERR2 TXREQ2 RTREN2
C2TR45CON TXEN5 TXABAT5 TXLARB5 TXERR5 TXREQ5 RTREN5 TX5PRI[1:0] TXEN4 TXABAT4 TXLARB4 TXERR4 TXREQ4 RTREN4
C2TR67CON TXEN7 TXABAT7 TXLARB7 TXERR7 TXREQ7 RTREN7 TX7PRI[1:0] TXEN6 TXABAT6 TXLARB6 TXERR6 TXREQ6 RTREN6
C2RXD Recieved Data Word
C2TXD Transmit Data Word
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
2007-2020 Microchip Technology Inc. DS70000185D-page 13
Table 3-6: CAN2 Register Map When C2CTRL1.WIN = 1
File Name Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2
See definition when WIN = x
C2BUFPNT1 F3BP[3:0] F2BP[3:0] F1BP[3:0] F0B
C2BUFPNT2 F7BP[3:0] F6BP[3:0] F5BP[3:0] F4B
C2BUFPNT3 F11BP[3:0] F10BP[3:0] F9BP[3:0] F8B
C2BUFPNT4 F15BP[3:0] F14BP[3:0] F13BP[3:0] F12B
C2RXM0SID SID[10:3] SID[2:0] — MIDE —
C2RXM0EID EID[15:8] EID[7:0]
C2RXM1SID SID[10:3] SID[2:0] — MIDE —
C2RXM1EID EID[15:8] EID[7:0]
C2RXM2SID SID[10:3] SID[2:0] — MIDE —
C2RXM2EID EID[15:8] EID[7:0]
C2RXF0SID SID[10:3] SID[2:0] — EXIDE —
C2RXF0EID EID[15:8] EID[7:0]
C2RXF1SID SID[10:3] SID[2:0] — EXIDE —
C2RXF1EID EID[15:8] EID[7:0]
C2RXF2SID SID[10:3] SID[2:0] — EXIDE —
C2RXF2EID EID[15:8] EID[7:0]
C2RXF3SID SID[10:3] SID[2:0] — EXIDE —
C2RXF3EID EID[15:8] EID[7:0]
C2RXF4SID SID[10:3] SID[2:0] — EXIDE —
C2RXF4EID EID[15:8] EID[7:0]
C2RXF5SID SID[10:3] SID[2:0] — EXIDE —
C2RXF5EID EID[15:8] EID[7:0]
C2RXF6SID SID[10:3] SID[2:0] — EXIDE —
C2RXF6EID EID[15:8] EID[7:0]
C2RXF7SID SID[10:3] SID[2:0] — EXIDE —
C2RXF7EID EID[15:8] EID[7:0]
C2RXF8SID SID[10:3] SID[2:0] — EXIDE —
C2RXF8EID EID[15:8] EID[7:0]
C2RXF9SID SID[10:3] SID[2:0] — EXIDE —
C2RXF9EID EID[15:8] EID[7:0]
C2RXF10SID SID[10:3] SID[2:0] — EXIDE —
C2RXF10EID EID[15:8] EID[7:0]
C2RXF11SID SID[10:3] SID[2:0] — EXIDE —
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
DS70000185D-page 14 2007-2020 Microchip Technology Inc.
C2RXF11EID EID[15:8] EID[7:0]
C2RXF12SID SID[10:3] SID[2:0] — EXIDE —
C2RXF12EID EID[15:8] EID[7:0]
C2RXF13SID SID[10:3] SID[2:0] — EXIDE —
C2RXF13EID EID[15:8] EID[7:0]
C2RXF14SID SID[10:3] SID[2:0] — EXIDE —
C2RXF14EID EID[15:8] EID[7:0]
C2RXF15SID SID[10:3] SID[2:0] — EXIDE —
C2RXF15EID EID[15:8] EID[7:0]
Table 3-6: CAN2 Register Map When C2CTRL1.WIN = 1 (Continued)
File Name Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
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DS70000185D-page 16 2007-2020 Microchip Technology Inc.
Register 4-2: CxCFG2: CAN Baud Rate Configuration Register 2
U-0 R/W-x U-0 U-0 U-0 R/W-x R/W-x R/W-x
— WAKFIL — — — SEG2PH[2:0]
bit 15 bit 8
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
SEG2PHTS SAM SEG1PH[2:0] PRSEG[2:0]
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 Unimplemented: Read as ‘0’
bit 14 WAKFIL: Select CAN Bus Line Filter for Wake-up bit
1 = Uses CAN bus line filter for wake-up
0 = CAN bus line filter is not used for wake-up
bit 13-11 Unimplemented: Read as ‘0’
bit 10-8 SEG2PH[2:0]: Phase Segment 2 bits
111 = Length is 8 x TQ
•
•
•
000 = Length is 1 x TQ
bit 7 SEG2PHTS: Phase Segment 2 Time Select bit
1 = Freely programmable
0 = Maximum of SEG1PH bits or Information Processing Time (IPT), whichever is greater
bit 6 SAM: Sample CAN Bus Line bit
1 = Bus line is sampled three times at the sample point
0 = Bus line is sampled once at the sample point
bit 5-3 SEG1PH[2:0]: Phase Segment 1 bits
111 = Length is 8 x TQ
•
•
•
000 = Length is 1 x TQ
bit 2-0 PRSEG[2:0]: Propagation Time Segment bits
111 = Length is 8 x TQ
•
•
•
000 = Length is 1 x TQ
2007-2020 Microchip Technology Inc. DS70000185D-page 17
Enhanced CAN Module
Register 4-3: CxFEN1: CAN Acceptance Filter Enable Register
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
FLTEN[15:8]
bit 15 bit 8
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
FLTEN[7:0]
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 FLTEN[15:0]: Enable Filter x bits
1 = Enables filter x to accept messages
0 = Disables filter x
Register 4-4: CxRXFnSID: CAN Acceptance Filter Standard Identifier Register n (n = 0-15)
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
SID[10:3]
bit 15 bit 8
R/W-x R/W-x R/W-x U-0 R/W-x U-0 R/W-x R/W-x
SID[2:0] — EXIDE — EID[17:16]
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-5 SID[10:0]: Standard Identifier bits
1 = Message address bit SIDx must be ‘1’ to match filter
0 = Message address bit SIDx must be ‘0’ to match filter
bit 4 Unimplemented: Read as ‘0’
bit 3 EXIDE: Extended Identifier Enable bit
If MIDE = 1:
1 = Matches only messages with Extended Identifier addresses
0 = Matches only messages with Standard Identifier addresses
If MIDE = 0:
Ignores EXIDE bit.
bit 2 Unimplemented: Read as ‘0’
bit 1-0 EID[17:16]: Extended Identifier bits
1 = Message address bit EIDx must be ‘1’ to match filter
0 = Message address bit EIDx must be ‘0’ to match filter
Note: If no mask is applied to a filter, the filter will only accept standard frames. The filter will not accept extended
frames even if the EXIDE bit is set to ‘1’.
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DS70000185D-page 18 2007-2020 Microchip Technology Inc.
Register 4-5: CxRXFnEID: CAN Acceptance Filter Extended Identifier Register n (n = 0-15)
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
EID[15:8]
bit 15 bit 8
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
EID[7:0]
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 EID[15:0]: Extended Identifier bits
1 = Message address bit EIDx must be ‘1’ to match filter
0 = Message address bit EIDx must be ‘0’ to match filter
Register 4-6: CxRXMnSID:
CAN
Acceptance Filter Mask Standard Identifier Register n (n = 0-2)
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
SID[10:3]
bit 15 bit 8
R/W-x R/W-x R/W-x U-0 R/W-x U-0 R/W-x R/W-x
SID[2:0] — MIDE — EID[17:16]
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-5 SID[10:0]: Standard Identifier bits
1 = Includes bit SIDx in filter comparison
0 = Bit SIDx is “don’t care” in filter comparison
bit 4 Unimplemented: Read as ‘0’
bit 3 MIDE: Identifier Receive Mode bit
1 = Matches only message types (standard or extended address) that correspond to EXIDE bit in filter
0 = Matches either standard or extended address message if filters match
(i.e., if (Filter SID) = (Message SID) or if (Filter SID/EID) = (Message SID/EID))
bit 2 Unimplemented: Read as ‘0’
bit 1-0 EID[17:16]: Extended Identifier bits
1 = Includes bit EIDx in filter comparison
0 = Bit EIDx is a “don’t care” in filter comparison
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Register 4-9: CxFMSKSEL2:
CAN
Filter 15-8 Mask Selection Register 2
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
F15MSK[1:0] F14MSK[1:0] F13MSK[1:0] F12MSK[1:0]
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
F11MSK[1:0] F10MSK[1:0] F9MSK[1:0] F8MSK[1:0]
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-14 F15MSK[1:0]: Mask Source for Filter 15 bits
11 = Reserved
10 = Acceptance Mask 2 registers contain mask
01 = Acceptance Mask 1 registers contain mask
00 = Acceptance Mask 0 registers contain mask
bit 13-12 F14MSK[1:0]: Mask Source for Filter 14 bits (same values as bits 15-14)
bit 11-10 F13MSK[1:0]: Mask Source for Filter 13 bits (same values as bits 15-14)
bit 9-8 F12MSK[1:0]: Mask Source for Filter 12 bits (same values as bits 15-14)
bit 7-6 F11MSK[1:0]: Mask Source for Filter 11 bits (same values as bits 15-14)
bit 5-4 F10MSK[1:0]: Mask Source for Filter 10 bits (same values as bits 15-14)
bit 3-2 F9MSK[1:0]: Mask Source for Filter 9 bits (same values as bits 15-14)
bit 1-0 F8MSK[1:0]: Mask Source for Filter 8 bits (same values as bits 15-14)
Register 4-10: CxBUFPNT1: CAN Filter 0-3 Buffer Pointer Register 1
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
F3BP[3:0] F2BP[3:0]
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
F1BP[3:0] F0BP[3:0]
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-12 F3BP[3:0]: RX Buffer Mask for Filter 3 bits
1111 = Filter hits received in RX FIFO buffer
1110 = Filter hits received in RX Buffer 14
•
•
•
0001 = Filter hits received in RX Buffer 1
0000 = Filter hits received in RX Buffer 0
bit 11-8 F2BP[3:0]: RX Buffer mask for Filter 2 bits (same values as bits 15-12)
bit 7-4 F1BP[3:0]: RX Buffer mask for Filter 1 bits (same values as bits 15-12)
bit 3-0 F0BP[3:0]: RX Buffer mask for Filter 0 bits (same values as bits 15-12)
2007-2020 Microchip Technology Inc. DS70000185D-page 21
Enhanced CAN Module
Register 4-11: CxBUFPNT2: CAN Filter 4-7 Buffer Pointer Register 2
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
F7BP[3:0] F6BP[3:0]
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
F5BP[3:0] F4BP[3:0]
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-12 F7BP[3:0]: RX Buffer Mask for Filter 7 bits
1111 = Filter hits received in RX FIFO buffer
1110 = Filter hits received in RX Buffer 14
•
•
•
0001 = Filter hits received in RX Buffer 1
0000 = Filter hits received in RX Buffer 0
bit 11-8 F6BP[3:0]: RX Buffer mask for Filter 6 bits (same values as bits 15-12)
bit 7-4 F5BP[3:0]: RX Buffer mask for Filter 5 bits (same values as bits 15-12)
bit 3-0 F4BP[3:0]: RX Buffer mask for Filter 4 bits (same values as bits 15-12)
Register 4-12: CxBUFPNT3: CAN Filter 8-11 Buffer Pointer Register 3
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
F11BP[3:0] F10BP[3:0]
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
F9BP[3:0] F8BP[3:0]
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-12 F11BP[3:0]: RX Buffer Mask for Filter 11
1111 = Filter hits received in RX FIFO buffer
1110 = Filter hits received in RX Buffer 14
•
•
•
0001 = Filter hits received in RX Buffer 1
0000 = Filter hits received in RX Buffer 0
bit 11-8 F10BP[3:0]: RX Buffer mask for Filter 10 (same values as bit 15-12)
bit 7-4 F9BP[3:0]: RX Buffer mask for Filter 9 (same values as bit 15-12)
bit 3-0 F8BP[3:0]: RX Buffer mask for Filter 8 (same values as bit 15-12)
2007-2020 Microchip Technology Inc. DS70000185D-page 23
Enhanced CAN Module
Register 4-15: CxRXFUL2: CAN Receive Buffer Full Register 2
R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0
RXFUL[31:24]
bit 15 bit 8
R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0
RXFUL[23:16]
bit 7 bit 0
Legend: C = Writable bit, but only ‘0’ can be written to clear the bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 RXFUL[31:16]: Receive Buffer n Full bits
1 = Buffer is full (set by module)
0 = Buffer is empty
Register 4-16: CxRXOVF1: CAN Receive Buffer Overflow Register 1
R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0
RXOVF[15:8]
bit 15 bit 8
R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0
RXOVF[7:0]
bit 7 bit 0
Legend: C = Writable bit, but only ‘0’ can be written to clear the bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 RXOVF[15:0]: Receive Buffer n Overflow bits
1 = Module attempted to write to a full buffer (set by module)
0 = No overflow condition
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DS70000185D-page 24 2007-2020 Microchip Technology Inc.
Register 4-17: CxRXOVF2: CAN Receive Buffer Overflow Register 2
R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0
RXOVF[31:24]
bit 15 bit 8
R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0
RXOVF[23:16]
bit 7 bit 0
Legend: C = Writable bit, but only ‘0’ can be written to clear the bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 RXOVF[31:16]: Receive Buffer n Overflow bits
1 = Module attempted to write to a full buffer (set by module)
0 = No overflow condition
2007-2020 Microchip Technology Inc. DS70000185D-page 25
Enhanced CAN Module
Register 4-18: CxFCTRL: CAN FIFO Control Register
R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0
DMABS[2:0] — — — — —
bit 15 bit 8
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — FSA[4:0]
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-13 DMABS[2:0]: DMA Buffer Size bits
111 = Reserved
110 = 32 buffers in DMA RAM
101 = 24 buffers in DMA RAM
100 = 16 buffers in DMA RAM
011 = 12 buffers in DMA RAM
010 = 8 buffers in DMA RAM
001 = 6 buffers in DMA RAM
000 = 4 buffers in DMA RAM
bit 12-5 Unimplemented: Read as ‘0’
bit 4-0 FSA[4:0]: FIFO Start Area bits
11111 = Reads buffer RB31
11110 = Reads buffer RB30
•
•
•
00010 = TX/RX buffer TRB2
00001 = TX/RX buffer TRB1
00000 = TX/RX buffer TRB0
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Register 4-19: CxFIFO: CAN FIFO Status Register
U-0 U-0 R-0 R-0 R-0 R-0 R-0 R-0
— — FBP[5:0]
bit 15 bit 8
U-0 U-0 R-0 R-0 R-0 R-0 R-0 R-0
— — FNRB[5:0]
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-14 Unimplemented: Read as ‘0’
bit 13-8 FBP[5:0]: FIFO Buffer Pointer bits
011111 = RB31 buffer
011110 = RB30 buffer
•
•
•
000001 = TRB1 buffer
000000 = TRB0 buffer
bit 7-6 Unimplemented: Read as ‘0’
bit 5-0 FNRB[5:0]: FIFO Next Read Buffer Pointer bits
011111 = RB31 buffer
011110 = RB30 buffer
•
•
•
000001 = TRB1 buffer
000000 = TRB0 buffer
2007-2020 Microchip Technology Inc. DS70000185D-page 27
Enhanced CAN Module
Register 4-20: CxINTF: CAN Interrupt Flag Register
U-0 U-0 R-0 R-0 R-0 R-0 R-0 R-0
— — TXBO TXBP RXBP TXWAR RXWAR EWARN
bit 15 bit 8
R/C-0 R/C-0 R/C-0 U-0 R/C-0 R/C-0 R/C-0 R/C-0
IVRIF WAKIF ERRIF — FIFOIF RBOVIF RBIF TBIF
bit 7 bit 0
Legend: C = Writable bit, but only ‘0’ can be written to clear the bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-14 Unimplemented: Read as ‘0’
bit 13 TXBO: Transmitter in Error State Bus Off bit
1 = Transmitter is in Bus Off state
0 = Transmitter is not in Bus Off state
bit 12 TXBP: Transmitter in Error State Bus Passive bit
1 = Transmitter is in Bus Passive state
0 = Transmitter is not in Bus Passive state
bit 11 RXBP: Receiver in Error Bus Passive bit
1 = Receiver is in Bus Passive state
0 = Receiver is not in Bus Passive state
bit 10 TXWAR: Transmitter in Error State Warning bit
1 = Transmitter is in Error Warning state
0 = Transmitter is not in Error Warning state
bit 9 RXWAR: Receiver in Error State Warning bit
1 = Receiver is in Error Warning state
0 = Receiver is not in Error Warning state
bit 8 EWARN: Transmitter or Receiver in Error State Warning bit
1 = Transmitter or receiver is in Error Warning state
0 = Transmitter or receiver is not in Error Warning state
bit 7 IVRIF: Invalid Message Interrupt Flag bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 6 WAKIF: Bus Wake-up Activity Interrupt Flag bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 5 ERRIF: Error Interrupt Flag bit (multiple sources in CxINTF[13:8] register)
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 4 Unimplemented: Read as ‘0’
bit 3 FIFOIF: FIFO Almost Full Interrupt Flag bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 2 RBOVIF: RX Buffer Overflow Interrupt Flag bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 1 RBIF: RX Buffer Interrupt Flag bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 0 TBIF: TX Buffer Interrupt Flag bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
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Register 4-21: CxINTE: CAN Interrupt Enable Register
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
IVRIE WAKIE ERRIE — FIFOIE RBOVIE RBIE TBIE
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-8 Unimplemented: Read as ‘0’
bit 7 IVRIE: Invalid Message Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 6 WAKIE: Bus Wake-up Activity Interrupt Flag bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 5 ERRIE: Error Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 4 Unimplemented: Read as ‘0’
bit 3 FIFOIE: FIFO Almost Full Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 2 RBOVIE: RX Buffer Overflow Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 1 RBIE: RX Buffer Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 0 TBIE: TX Buffer Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
2007-2020 Microchip Technology Inc. DS70000185D-page 29
Enhanced CAN Module
Register 4-22: CxVEC: CAN Interrupt Code Register
U-0 U-0 U-0 R-0 R-0 R-0 R-0 R-0
— — — FILHIT[4:0]
bit 15 bit 8
U-0 R-1 R-0 R-0 R-0 R-0 R-0 R-0
— ICODE[6:0]
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-13 Unimplemented: Read as ‘0’
bit 12-8 FILHIT[4:0]: Filter Hit Number bits
10000-11111 = Reserved
01111 = Filter 15
•
•
•
00001 = Filter 1
00000 = Filter 0
bit 7 Unimplemented: Read as ‘0’
bit 6-0 ICODE[6:0]: Interrupt Flag Code bits
1000101-1111111 = Reserved
1000100 = FIFO almost full interrupt
1000011 = Receiver overflow interrupt
1000010 = Wake-up interrupt
1000001 = Error interrupt
1000000 = No interrupt
•
•
•
0100000-0111111 = Reserved
0011111 = RB31 buffer interrupt
0011110 = RB30 buffer interrupt
•
•
•
0001001 = RB9 buffer interrupt
0001000 = RB8 buffer interrupt
0000111 = TRB7 buffer interrupt
0000110 = TRB6 buffer interrupt
0000101 = TRB5 buffer interrupt
0000100 = TRB4 buffer interrupt
0000011 = TRB3 buffer interrupt
0000010 = TRB2 buffer interrupt
0000001 = TRB1 buffer interrupt
0000000 = TRB0 buffer interrupt
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Register 4-23: CxCTRL1: CAN Control Register 1
U-0 U-0 R/W-0 R/W-0 r-0 R/W-1 R/W-0 R/W-0
— — CSIDL ABAT — REQOP[2:0]
bit 15 bit 8
R-1 R-0 R-0 U-0 R/W-0 U-0 U-0 R/W-0
OPMODE[2:0] — CANCAP — — WIN
bit 7 bit 0
Legend: r = Reserved bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-14 Unimplemented: Read as ‘0’
bit 13 CSIDL: Stop in Idle Mode bit
1 = Discontinues module operation when device enters Idle mode
0 = Continues module operation in Idle mode
bit 12 ABAT: Abort All Pending Transmissions bit
1 = Signals all transmit buffers to abort transmission
0 = Module will clear this bit when all transmissions are aborted
bit 11 Reserved: Do not use
bit 10-8 REQOP[2:0]: Request Operation Mode bits
111 = Set Listen All Messages mode
110 = Reserved
101 = Reserved
100 = Set Configuration mode
011 = Set Listen-Only Mode
010 = Set Loopback mode
001 = Set Disable mode
000 = Set Normal Operation mode
bit 7-5 OPMODE[2:0]: Operation Mode bits
111 = Module is in Listen All Messages mode
110 = Reserved
101 = Reserved
100 = Module is in Configuration mode
011 = Module is in Listen-Only mode
010 = Module is in Loopback mode
001 = Module is in Disable mode
000 = Module is in Normal Operation mode
bit 4 Unimplemented: Read as ‘0’
bit 3 CANCAP: CAN Message Receive Timer Capture Event Enable bit
1 = Enables input capture based on CAN message receive
0 = Disables CAN capture
bit 2-1 Unimplemented: Read as ‘0’
bit 0 WIN: SFR Map Window Select bit
1 = Uses filter window
0 = Uses buffer window
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Register 4-25: CxTRmnCON: CAN TX/RX Buffer m Control Register (m = 0,2,4,6; n = 1,3,5,7)
R/W-0 R-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0
TXENn TXABTn TXLARBn TXERRn TXREQn RTRENn TXnPRI[1:0]
bit 15 bit 8
R/W-0 R-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0
TXENm TXABTm( )1TXLARBm( )1TXERRm( )1TXREQm RTRENm TXmPRI[1:0]
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-8 Refer to definition for bits 7-0, Controls Buffer n
bit 7 TXENm: TX/RX Buffer Selection bit
1 = Buffer TRBn is a transmit buffer
0 = Buffer TRBn is a receive buffer
bit 6 TXABTm: Message Aborted bit( )1
1 = Message was aborted
0 = Message completed transmission successfully
bit 5 TXLARBm: Message Lost Arbitration bit( )1
1 = Message lost arbitration while being sent
0 = Message did not lose arbitration while being sent
bit 4 TXERRm: Error Detected During Transmission bit( )1
1 = A bus error occurred while the message was being sent
0 = A bus error did not occur while the message was being sent
bit 3 TXREQm: Message Send Request bit
1 = Requests that a message be sent; the bit automatically clears when the message is successfully sent
0 = Clearing the bit to ‘0’ while set requests a message abort
bit 2 RTRENm: Auto-Remote Transmit Enable bit
1 = When a remote transmit is received, TXREQ is set
0 = When a remote transmit is received, TXREQ is unaffected
bit 1-0 TXmPRI[1:0]: Message Transmission Priority bits
11 = Highest message priority
10 = High intermediate message priority
01 = Low intermediate message priority
00 = Lowest message priority
Note 1: This bit is cleared when TXREQ is set.
2007-2020 Microchip Technology Inc. DS70000185D-page 33
Enhanced CAN Module
Register 4-26: CxEC: CAN Transmit/Receive Error Count Register
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
TERRCNT[7:0]
bit 15 bit 8
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
RERRCNT[7:0]
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-8 TERRCNT[7:0]: Transmit Error Count bits
bit 7-0 RERRCNT[7:0]: Receive Error Count bits
Register 4-27: CxRXD: CAN Receive Data Register
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
DATA[15:8]
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
DATA[7:0]
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 DATA[15:0]: Received Data Word bits
Register 4-28: CxTXD: CAN Transmit Data Register
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
DATA[15:8]
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
DATA[7:0]
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 DATA[15:0]: Transmitted Data Word bits
dsPIC33F/PIC24H Family Reference Manual
DS70000185D-page 34 2007-2020 Microchip Technology Inc.
5.0 CAN MESSAGE BUFFERS
CAN message buffers are located in DMA RAM. They are not CAN Special Function Registers.
The user application must directly write into the DMA RAM area that is configured for CAN
message buffers. The location and size of the buffer area is defined by the user application.
This section provides information on how the message buffer words are organized for transmission
and reception. (Refer to Section 2.0 “CAN Message Formats” for message buffer layout details
and Section 10.0 “DMA Controller Configuration” for details on how to configure CAN message
buffers in DMA RAM.)
Buffer 5-1:
CAN
Message Buffer Word 0
U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x
— — — SID[10:6]
bit 15 bit 8
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
SID[5:0] SRR IDE
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-13 Unimplemented: Read as ‘0’
bit 12-2 SID[10:0]: Standard Identifier bits
bit 1 SRR: Substitute Remote Request bit
When IDE = :0
1 = Message will request remote transmission
0 = Normal message
When IDE = :1
The SRR bit must be set to ‘1’
bit 0 IDE: Extended Identifier bit
1 = Message will transmit Extended Identifier
0 = Message will transmit Standard Identifier
Buffer 5-2:
CAN
Message Buffer Word 1
U-0 U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x
— — — — EID[17:14]
bit 15 bit 8
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
EID[13:6]
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-12 Unimplemented: Read as ‘0’
bit 11-0 EID[17:6]: Extended Identifier bits

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Kategori: Inte kategoriserad
Modell: dsPIC33FJ256MC510

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