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2007-2020 Microchip Technology Inc. DS70000185D-page 1
HIGHLIGHTS
This section of the manual contains the following major topics:
1.0 Introduction ....................................................................................................................... 2
2.0 CAN Message Formats..................................................................................................... 4
3.0 Register Maps................................................................................................................... 8
4.0 CAN Registers ................................................................................................................ 15
5.0 CAN Message Buffers .................................................................................................... 34
6.0 Bit Timing ........................................................................................................................ 38
7.0 CAN Operating Modes.................................................................................................... 42
8.0 Transmitting CAN Messages .......................................................................................... 43
9.0 Receiving CAN Messages .............................................................................................. 50
10.0 DMA Controller Configuration ......................................................................................... 63
11.0 CAN Error Management ................................................................................................. 66
12.0 CAN Interrupts ................................................................................................................ 69
13.0 CAN Low-Power Modes.................................................................................................. 72
14.0 CAN Time Stamping Using Input Capture ...................................................................... 72
15.0 Related Application Notes............................................................................................... 73
16.0 Revision History .............................................................................................................. 74
Enhanced Controller Area Network (CAN)
dsPIC33F/PIC24H Family Reference Manual
DS70000185D-page 2 2007-2020 Microchip Technology Inc.
1.0 INTRODUCTION
The dsPIC33F/PIC24H Enhanced Controller Area Network (CAN) module implements the CAN
Protocol 2.0B, used primarily in industrial and automotive applications. This asynchronous serial
data communication protocol provides reliable communications in electrically noisy environ-
ments. The dsPIC33F device family integrates up to two CAN modules. Figure 1-1 illustrates a
typical CAN bus topology.
Figure 1-1: Typical CAN Bus Network
The CAN module supports the following key features:
Standards Compliance:
• Full CAN 2.0B compliance
• Programmable bit rate up to 1 Mbps
Message Reception:
• 32 message buffers – all of them can be used for reception
• 16 acceptance filters for message filtering
• Three acceptance filter mask registers for message filtering
• Automatic response to Remote Transmit Request
• Up to 32-message deep First-In First-Out (FIFO) buffer
• DeviceNet™ addressing support
• DMA interface for message reception
Note: This family reference manual section is meant to serve as a complement to device
data sheets. Depending on the device variant, this manual section may not apply to
all dsPIC33/PIC24 devices.
Please consult the note at the beginning of the “Direct Memory Access (DMA)”
chapter in the current device data sheet to check whether this document supports
the device you are using.
Device data sheets and family reference manual sections are available for
download from the Microchip Worldwide Website at: http://www.microchip.com
CAN
bus
CAN1
PIC® MCU
with Integrated
CAN
CAN
Transceiver
dsPIC33F/PIC24H
with Integrated
CAN™
dsPIC33/PIC24
with Integrated
CAN
Transceiver
CAN Transceiver
CAN
Transceiver
CAN
CAN2
CAN
Transceiver
dsPIC33F/PIC24H
2007-2020 Microchip Technology Inc. DS70000185D-page 3
Enhanced CAN Module
Message Transmission:
• Eight message buffers configurable for message transmission
• User-defined priority levels for message buffers used for transmission
• DMA interface for message transmission
Others:
• Loopback, Listen All Messages and Listen Only modes for self-test, system diagnostics
and bus monitoring
• Low-power operating modes
Figure 1-2 illustrates the general structure of the CAN module and its interaction with the DMA
Controller and DMA RAM.
Figure 1-2: CAN Interaction with DMA
1.1 CAN Module
The CAN module consists of a protocol engine, message acceptance filters, and separate trans-
mit and receive DMA interfaces. The protocol engine transmits and receives messages to and
from the CAN bus (as per CAN bus 2.0B protocol). The user-configurable acceptance filters are
used by the module to examine the received message to determine if it should be stored in the
DMA message buffer or discarded.
For received messages, the receive DMA interface generates a receive data interrupt to initiate
a DMA cycle. The receive DMA channel reads data from the CxRXD register and writes them
into the message buffer.
For transmit messages, the transmit DMA interface generates a transmit data interrupt to start a
DMA cycle. The transmit DMA channel reads from the message buffer and writes to the CxTXD
register for message transmission.
1.2 Message Buffers
The CAN module supports up to 32 message buffers for storing data transmitted or received on
the CAN bus. These buffers are located in DMA RAM. Message Buffers 0-7 can be configured
for either transmit or receive operation. Message Buffers 8-31 are receive-only buffers and
cannot be used for message transmission.
1.3 DMA Controller
The DMA controller acts as an interface between the message buffers and CAN to transfer data
back and forth without CPU intervention. The DMA controller supports up to eight channels for
transferring data between DMA RAM and the dsPIC33F peripherals. Two separate DMA
channels are needed to support CAN message transmission and CAN message reception.
Each DMA channel has a DMA Request (DMAxREQ) register, which is used by the user
application to assign an interrupt event to trigger a DMA-based message transfer.
CxTX
CxRX
Message Buffer 0
Message Buffer 7
Message Buffer 8
Message Buffer 31
CAN
Protocol
Engine
CAN
Transmit
Register
(CxTXD)
Acceptance
Filter 0-15
CAN
Receive
Register
(CxRXD)
TX DMA
Interface
RX DMA
Interface
DMA
Channel
DMA
Channel
Message Buffer 1
CAN Module Message Buffer
(DMA RAM)
RX
Request
TX
Request

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Modell: dsPIC33FJ64GP802

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