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2003-2021 Microchip Technology Inc. DS20001801K-page 1
MCP2515
Features
• Implements CAN V2.0B at 1 Mb/s:
- 0 to 8-byte length in the data field
- Standard and extended data and remote
frames
• Receive Buffers, Masks and Filters:
- Two receive buffers with prioritized message
storage
- Six 29-bit filters
- Two 29-bit masks
• Data Byte Filtering on the First Two Data Bytes
(applies to standard data frames)
• Three Transmit Buffers with Prioritization and
Abort Features
• High-Speed SPI Interface (10 MHz):
- SPI Modes 0,0 and 1,1
• One-Shot mode Ensures Message Transmission
is Attempted Only One Time
• Clock Out Pin with Programmable Prescaler:
- Can be used as a clock source for other
device(s)
• Start-of-Frame (SOF) Signal is Available for
Monitoring the SOF Signal:
- Can be used for time slot-based protocols
and/or bus diagnostics to detect early bus
degradation
• Interrupt Output Pin with Selectable Enables
• Buffer Full Output Pins Configurable as:
- Interrupt output for each receive buffer
- General purpose output
• Request-to-Send (RTS) Input Pins Individually
Configurable as:
- Control pins to request transmission for each
transmit buffer
- General purpose inputs
• Low-Power CMOS Technology:
- Operates from 2.7V-5.5V
- 5 mA active current (typical)
- 1 µA standby current (typical) (Sleep mode)
• Temperature Ranges Supported:
- Industrial (I): -40°C to +85°C
- Extended (E): -40°C to +125°C
• AEC-Q100 Qualified
Description
Microchip Technology’s MCP2515 is a stand-alone
Controller Area Network (CAN) controller that imple-
ments the CAN specification, Version 2.0B. It is capable
of transmitting and receiving both standard and
extended data and remote frames. The MCP2515 has
two acceptance masks and six acceptance filters that
are used to filter out unwanted messages, thereby
reducing the host MCU’s overhead. The MCP2515
interfaces with microcontrollers (MCUs) via an industry
standard Serial Peripheral Interface (SPI).
Package Types
16
5
TXCAN
RXCAN
VDD
RESET
CS
SO
MCP2515
1
2
3
4
18
17
16
15
SI
SCK
INT
RX0BF
14
13
12
11
RX1BF10
OSC2
OSC1
CLKOUT/SOF
TX2RTS
5
6
7
8
VSS 9
TX0RTS
TX1RTS
TXCAN
RXCAN
TX0RTS
OSC1
CLKOUT/SOF
OSC2
CS
VDD
RESET
SO
SCK
INT
SI
RX0BF
RX1BF
VSS
TX1RTS
TX2RTS
NC NC
18-Lead PDIP/SOIC
20-Lead TSSOP
2
NC
TX2RTS
TX0RTS
SO
SI
OSC2
NC
OSC1
GND
RX1BF
SCK
RXCAN
TXCAN
VDD
RESET
TX1RTS
EP
20
1
19 18 17
3
4
14
13
12
11
6 7 8 9
21
10
15
CLKOUT
CS
INT
RX0BF
* Includes Exposed Thermal Pad (EP); see Table 1-1.
13
12
1
2
3
4
5
6
7
8
9
20
19
18
17
16
15
14
11
10
MCP2515
20-Lead QFN*
Stand-Alone CAN Controller with SPI Interface
MCP2515
DS20001801K-page 2 2003-2021 Microchip Technology Inc.
NOTES:
2003-2021 Microchip Technology Inc. DS20001801K-page 3
MCP2515
1.0 DEVICE OVERVIEW
The MCP2515 is a stand-alone CAN controller devel-
oped to simplify applications that require interfacing
with a CAN bus. A simple block diagram of the
MCP2515 is shown in Figure 1-1. The device consists
of three main blocks:
1. The CAN module, which includes the CAN
protocol engine, masks, filters, transmit and
receive buffers.
2. The control logic and registers that are used to
configure the device and its operation.
3. The SPI protocol block.
An example system implementation using the device is
shown in Figure 1-2.
1.1 CAN Module
The CAN module handles all functions for receiving and
transmitting messages on the CAN bus. Messages are
transmitted by first loading the appropriate message buf-
fer and control registers. Transmission is initiated by
using control register bits via the SPI interface or by
using the transmit enable pins. Status and errors can be
checked by reading the appropriate registers. Any
message detected on the CAN bus is checked for errors
and then matched against the user-defined filters to see
if it should be moved into one of the two receive buffers.
1.2 Control Logic
The control logic block controls the setup and operation
of the MCP2515 by interfacing to the other blocks in
order to pass information and control.
Interrupt pins are provided to allow greater system
flexibility. There is one multipurpose interrupt pin (as
well as specific interrupt pins) for each of the receive
registers that can be used to indicate a valid message
has been received and loaded into one of the receive
buffers. Use of the specific interrupt pins is optional.
The general purpose interrupt pin, as well as status
registers (accessed via the SPI interface), can also be
used to determine when a valid message has been
received.
Additionally, there are three pins available to initiate
immediate transmission of a message that has been
loaded into one of the three transmit registers. Use of
these pins is optional, as initiating message transmis-
sions can also be accomplished by utilizing control
registers accessed via the SPI interface.
1.3 SPI Protocol Block
The MCU interfaces to the device via the SPI interface.
Writing to, and reading from, all registers is
accomplished using standard SPI read and write
commands, in addition to specialized SPI commands.
FIGURE 1-1: BLOCK DIAGRAM
SPI
Interface
Logic
SPI
Bus
INT
CS
SCK
SI
SO
CAN
Protocol
Engine
RXCAN
TXCAN
Control Logic
RX0BF
RX1BF
TX0RTS
TX1RTS
TX2RTS
TX and RX Buffers
Masks and Filters
CAN Module
RESET
Timing
Generation
OSC1
OSC2
CLKOUT
Control
and
Interrupt
Registers

Produktspecifikationer

Varumärke: Microchip
Kategori: Inte kategoriserad
Modell: MCP2515

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