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2003 Microchip Technology Inc. DS11195C-page 1
MMCP41XXX/42XXX
Features
256 taps for each potentiometer
Potentiometer values for 10 k, 50 k and
100 k
Single and dual versions
SPI™ serial interface (mode 0,0 and 1,1)
±1 LSB max INL & DNL
Low power CMOS technology
1 µA maximum supply current in static operation
Multiple devices can be daisy-chained together
(MCP42XXX only)
Shutdown feature open circuits of all resistors for
maximum power savings
Hardware shutdown pin available on MCP42XXX
only
Single supply operation (2.7V - 5.5V)
Industrial temperature range: -40°C to +85°C
Extended temperature range: -40°C to +125°C
Block Diagram
Description
The MCP41XXX and MCP42XXX devices are 256-
position, digital potentiometers available in 10 k,
50 k and 100 k resistance versions. The
MCP41XXX is a single-channel device and is offered in
an 8-pin PDIP or SOIC package. The MCP42XXX con-
tains two independent channels in a 14-pin PDIP, SOIC
or TSSOP package. The wiper position of the
MCP41XXX/42XXX varies linearly and is controlled via
an industry-standard SPI interface. The devices con-
sume <1 µA during static operation. A software shut-
down feature is provided that disconnects the “A”
terminal from the resistor stack and simultaneously con-
nects the wiper to the “B” terminal. In addition, the dual
MCP42XXX has a SHDN pin that performs the same
function in hardware. During shutdown mode, the con-
tents of the wiper register can be changed and the
potentiometer returns from shutdown to the new value.
The wiper is reset to the mid-scale position (80h) upon
power-up. The RS (reset) pin implements a hardware
reset and also returns the wiper to mid-scale. The
MCP42XXX SPI interface includes both the SI and SO
pins, allowing daisy-chaining of multiple devices. Chan-
nel-to-channel resistance matching on the MCP42XXX
varies by less than 1%. These devices operate from a
single 2.7 - 5.5V supply and are specified over the
extended and industrial temperature ranges.
Package Types
16-Bit
Shift
VDD
VSS
SI
SCK
RS SHDN
PB1
PA1
PW1
Resistor
Array 1*
Wiper
Register
PB0
PW0
PA0
Resistor
Array 0
Wiper
Register
Register
S0
Control
Logic
CS
*Potentiometer P1 is only available on the dual
MCP42XXX version.
MCP42XXX
1
2
3
411
12
13
14
8
9
10
5
6
7
PDIP/SOIC/TSSOP
PB1
PA1
PW1
SHDN
SO
RS
PW0
PB0
CS
PA0
SCK
SI
VSS
VDD
MCP41XXX
1
2
3
45
6
7
8
PDIP/SOIC
PB0
PA0
VDD
PW0
VSS
CS
SCK
SI
Single/Dual Digital Potentiometer with SPI Interface
MCP41XXX/42XXX
DS11195C-page 2 2003 Microchip Technology Inc.
1.0 ELECTRICAL CHARACTERISTICS
DC CHARACTERISTICS: 10 k VERSION
Electrical Characteristics: Unless otherwise indicated, V DD = +2.7V to 5.5V, TA = -40°C to +85°C (TSSOP devices are only specified at +25°C and
+85°C). Typical specifications represent values for V DD = 5V, VSS = 0V, VB = 0V, TA = +25°C.
Parameters Sym Min Typ Max Units Conditions
Rheostat Mode
Nominal Resistance R 8 10 12 kTA = +25°C (Note 1)
Rheostat Differential Non Linearity R-DNL -1 ±1/4 +1 LSB Note 2
Rheostat Integral Non Linearity R-INL -1 ±1/4 +1 LSB Note 2
Rheostat Tempco RAB/T 800 — ppm/°C
Wiper Resistance RW 52 100 VDD = 5.5V, IW = 1 mA, code 00h
R
W 73 125 VDD = 2.7V, IW = 1 mA, code 00h
Wiper Current IW-1 +1 mA
Nominal Resistance Match R/R 0.2 1 % MCP42010 only, P0 to P1; T A = +25°C
Potentiometer Divider
Resolution N 8 — Bits
Monotonicity N 8 — Bits
Differential Non-Linearity DNL -1 ±1/4 +1 LSB Note 3
Integral Non-Linearity INL -1 ±1/4 +1 LSB Note 3
Voltage Divider Tempco VW/T 1 ppm/°C Code 80h
Full Scale Error VWFSE -2 -0.7 0 LSB Code FFh, V DD
= 5V, see Figure 2-25
VWFSE -2 -0.7 0 LSB Code FFh, V DD
= 3V, see Figure 2-25
Zero Scale Error VWZSE 0 +0.7 +2 LSB Code 00h, V DD = 5V, see Figure 2-25
VWZSE 0 +0.7 +2 LSB Code 00h, V DD = 3V, see Figure 2-25
Resistor Terminals
Voltage Range VA,B,W 0 — VDD Note 4
Capacitance (CA or CB) 15 pF f = 1 MHz, Code = 80h, see Figure 2-30
Capacitance CW 5.6 pF f = 1 MHz, Code = 80h, see Figure 2-30
Dynamic Characteristics (All dynamic characteristics use V DD = 5V)
Bandwidth -3dB BW 1 MHz VB = 0V, Measured at Code 80h,
Output Load = 30 PF
Settling Time tS 2 µS V
A = VDD,VB = 0V, ±1% Error Band, Transition
from Code 00h to Code 80h, Output Load = 30 pF
Resistor Noise Voltage e NWB 9 — nV/Hz V
A = Open, Code 80h, f =1 kHz
Crosstalk CT— -95 — dB VA = VDD, VB = 0V (Note 5)
Digital Inputs/Outputs (CS , SCK, SI, SO) See Figure 2-12 for RS and SHDN pin operation
Schmitt Trigger High-Level Input Voltage V IH 0.7VDD ——V
Schmitt Trigger Low-Level Input Voltage V IL — 0.3VDD V
Hysteresis of Schmitt Trigger Inputs VHYS — 0.05VDD
Low-Level Output Voltage VOL 0.40 V IOL = 2.1 mA, V
DD = 5V
High-Level Output Voltage V OH VDD
- 0.5 V IOH = -400 µA, VDD = 5V
Input Leakage Current ILI -1 +1 µA CS = V DD, VIN = VSS or VDD, includes VA SHDN=0
Pin Capacitance (All inputs/outputs) C IN
, COUT 10 pF VDD = 5.0V, TA = +25°C, f c = 1 MHz
Power Requirements
Operating Voltage Range V DD 2.7 — 5.5 V
Supply Current, Active IDDA 340 500 µA VDD = 5.5V, CS = VSS , fSCK = 10 MHz,
SO = Open, Code FFh (Note 6)
Supply Current, Static IDDS 0.01 1 µA CS, SHDN, RS = V DD = 5.5V, SO = Open (Note 6)
Power Supply Sensitivity PSS 0.0015 0.0035 %/% VDD = 4.5V - 5.5V, VA
= 4.5V, Code 80h
PSS 0.0015 0.0035 %/% VDD = 2.7V - 3.3V, VA
= 2.7V, Code 80h
Note 1: VAB
= V
DD , no connection on wiper.
2: Rheostat position non-linearity R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum
resistance wiper positions. R-DNL measures the relative step change from the ideal between successive tap positions. I W = 50 µA for
VDD = 3V and IW = 400 µA for VDD = 5V for 10 k version. See Figure 2-26 for test circuit.
3: INL and DNL are measured at VW with the device configured in the voltage divider or potentiometer mode. V A = V
DD and VB = 0V. DNL
specification limits of ±1 LSB max are specified monotonic operating conditions. See Figure 2-25 for test circuit.
4: Resistor terminals A,B and W have no restrictions on polarity with respect to each other. Full-scale and zero-scale error were measured
using Figure 2-25.
5: Measured at VW pin where the voltage on the adjacent V W pin is swinging full-scale.
6: Supply current is independent of current through the potentiometers.
2003 Microchip Technology Inc. DS11195C-page 3
MCP41XXX/42XXX
DC CHARACTERISTICS: 50 k VERSION
Electrical Characteristics: Unless otherwise indicated, V DD = +2.7V to 5.5V, TA = -40°C to +85°C (TSSOP devices are only specified at +25°C and
+85°C). Typical specifications represent values for V DD = 5V, VSS = 0V, VB = 0V, T
A = +25°C.
Parameters Sym Min Typ Max Units Conditions
Rheostat Mode
Nominal Resistance R 35 50 65 kTA = +25°C (Note 1)
Rheostat Differential Non-Linearity R-DNL -1 ±1/4 +1 LSB Note 2
Rheostat Integral Non-Linearity R-INL -1 ±1/4 +1 LSB Note 2
Rheostat Tempco RAB/T 800 — ppm/°C
Wiper Resistance RW 125 175 VDD = 5.5V, IW = 1 mA, code 00h
R
W 175 250 VDD = 2.7V, IW = 1 mA, code 00h
Wiper Current IW-1 +1 mA
Nominal Resistance Match R/R 0.2 1 % MCP42050 only, P0 to P1;T A = +25°C
Potentiometer Divider
Resolution N 8 — Bits
Monotonicity N 8 — Bits
Differential Non-Linearity DNL -1 ±1/4 +1 LSB Note 3
Integral Non-Linearity INL -1 ±1/4 +1 LSB Note 3
Voltage Divider Tempco VW/T 1 ppm/°C Code 80h
Full-Scale Error VWFSE -1 -0.25 0 LSB Code FFh, V DD
= 5V, see Figure 2-25
VWFSE -1 -0.35 0 LSB Code FFh, V DD
= 3V, see Figure 2-25
Zero-Scale Error VWZSE 0 +0.25 +1 LSB Code 00h, V DD = 5V, see Figure 2-25
VWZSE 0 +0.35 +1 LSB Code 00h, V DD = 3V, see Figure 2-25
Resistor Terminals
Voltage Range VA,B,W 0 — VDD Note 4
Capacitance (CA or CB) 11 pF f =1 MHz, Code = 80h, see Figure 2-30
Capacitance CW 5.6 pF f =1 MHz, Code = 80h, see Figure 2-30
Dynamic Characteristics (All dynamic characteristics use V DD = 5V)
Bandwidth -3dB BW 280 MHz VB = 0V, Measured at Code 80h,
Output Load = 30 PF
Settling Time tS 8 µS V
A = VDD,VB = 0V, ±1% Error Band, Transition
from Code 00h to Code 80h, Output Load = 30 pF
Resistor Noise Voltage e NWB 20 — nV/Hz VA = Open, Code 80h, f =1 kHz
Crosstalk CT— -95 — dB VA = VDD, VB = 0V (Note 5)
Digital Inputs/Outputs (CS , SCK, SI, SO) See Figure 2-12 for RS and SHDN pin operation.
Schmitt Trigger High-Level Input Voltage V IH 0.7VDD ——V
Schmitt Trigger Low-Level Input Voltage V IL — 0.3VDD V
Hysteresis of Schmitt Trigger Inputs VHYS — 0.05VDD
Low-Level Output Voltage VOL 0.40 V IOL = 2.1 mA, V
DD = 5V
High-Level Output Voltage V OH VDD
- 0.5 V IOH = -400 µA, VDD = 5V
Input Leakage Current ILI -1 +1 µA CS = VDD, VIN = VSS or VDD , includes V
A SHDN=0
Pin Capacitance (All inputs/outputs) C IN
, COUT 10 pF VDD = 5.0V, TA = +25°C, f c = 1 MHz
Power Requirements
Operating Voltage Range V DD 2.7 — 5.5 V
Supply Current, Active IDDA 340 500 µA VDD = 5.5V, CS = VSS , fSCK = 10 MHz,
SO = Open, Code FFh (Note 6)
Supply Current, Static IDDS 0.01 1 µA CS, SHDN, RS = V DD = 5.5V, SO = Open (Note 6)
Power Supply Sensitivity PSS 0.0015 0.0035 %/% VDD = 4.5V - 5.5V, VA
= 4.5V, Code 80h
PSS 0.0015 0.0035 %/% VDD = 2.7V - 3.3V, VA
= 2.7V, Code 80h
Note 1: VAB
= V
DD , no connection on wiper.
2: Rheostat position non-linearity R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum
resistance wiper positions. R-DNL measures the relative step change from the ideal between successive tap positions. I W = VDD/R for
+3V or +5V for 50 k version. See Figure 2-26 for test circuit.
3: INL and DNL are measured at VW with the device configured in the voltage divider or potentiometer mode. V A = V
DD and VB = 0V. DNL
specification limits of ±1 LSB max are specified monotonic operating conditions. See Figure 2-25 for test circuit.
4: Resistor terminals A,B and W have no restrictions on polarity with respect to each other. Full-scale and zero-scale error were measured
using Figure 2-25.
5: Measured at VW pin where the voltage on the adjacent V W pin is swinging full scale.
6: Supply current is independent of current through the potentiometers.
MCP41XXX/42XXX
DS11195C-page 4 2003 Microchip Technology Inc.
DC CHARACTERISTICS: 100 k VERSION
Electrical Characteristics: Unless otherwise indicated, V DD = +2.7V to 5.5V, TA = -40°C to +85°C (TSSOP devices are only specified at +25°C and
+85°C). Typical specifications represent values for V DD = 5V, VSS = 0V, VB = 0V, T
A = +25°C.
Parameters Sym Min Typ Max Units Conditions
Rheostat Mode
Nominal Resistance R 70 100 130 kTA = +25°C (Note 1)
Rheostat Differential Non-Linearity R-DNL -1 ±1/4 +1 LSB Note 2
Rheostat Integral Non-Linearity R-INL -1 ±1/4 +1 LSB Note 2
Rheostat Tempco RAB/T 800 — ppm/°C
Wiper Resistance RW 125 175 VDD = 5.5V, IW = 1 mA, code 00h
R
W 175 250 VDD = 2.7V, IW = 1 mA, code 00h
Wiper Current IW-1 +1 mA
Nominal Resistance Match R/R 0.2 1 % MCP42010 only, P0 to P1;T A = +25°C
Potentiometer Divider
Resolution N 8 — Bits
Monotonicity N 8 — Bits
Differential Non-Linearity DNL -1 ±1/4 +1 LSB Note 3
Integral Non-Linearity INL -1 ±1/4 +1 LSB Note 3
Voltage Divider Tempco VW/T 1 ppm/°C Code 80h
Full-Scale Error VWFSE -1 -0.25 0 LSB Code FFh, V DD
= 5V, see Figure 2-25
VWFSE -1 -0.35 0 LSB Code FFh, V DD
= 3V, see Figure 2-25
Zero-Scale Error VWZSE 0 +0.25 +1 LSB Code 00h, V DD = 5V, see Figure 2-25
VWZSE 0 +0.35 +1 LSB Code 00h, V DD = 3V, see Figure 2-25
Resistor Terminals
Voltage Range VA,B,W 0 — VDD Note 4
Capacitance (CA or CB) 11 pF f =1 MHz, Code = 80h, see Figure 2-30
Capacitance CW 5.6 pF f =1 MHz, Code = 80h, see Figure 2-30
Dynamic Characteristics (All dynamic characteristics use V DD = 5V.)
Bandwidth -3dB BW 145 MHz VB = 0V, Measured at Code 80h,
Output Load = 30 PF
Settling Time tS 18 µS V
A = VDD,VB = 0V, ±1% Error Band, Transition
from Code 00h to Code 80h, Output Load = 30 pF
Resistor Noise Voltage e NWB 29 — nV/Hz VA = Open, Code 80h, f =1 kHz
Crosstalk CT— -95 — dB VA = VDD, VB = 0V (Note 5)
Digital Inputs/Outputs (CS , SCK, SI, SO) See Figure 2-12 for RS and SHDN pin operation.
Schmitt Trigger High-Level Input Voltage V IH 0.7VDD ——V
Schmitt Trigger Low-Level Input Voltage V IL — 0.3VDD V
Hysteresis of Schmitt Trigger Inputs VHYS — 0.05VDD
Low-Level Output Voltage VOL 0.40 V IOL = 2.1 mA, V
DD = 5V
High-Level Output Voltage V OH VDD
- 0.5 V I OH = -400 µA, VDD = 5V
Input Leakage Current ILI -1 +1 µA CS = VDD, VIN = VSS or VDD
, includes VA SHDN=0
Pin Capacitance (All inputs/outputs) C IN
, COUT 10 pF VDD = 5.0V, TA = +25°C, f c = 1 MHz
Power Requirements
Operating Voltage Range V DD 2.7 — 5.5 V
Supply Current, Active IDDA 340 500 µA VDD = 5.5V, CS = VSS , fSCK = 10 MHz,
SO = Open, Code FFh (Note 6)
Supply Current, Static IDDS 0.01 1 µA CS, SHDN, RS = V DD = 5.5V, SO = Open (Note 6)
Power Supply Sensitivity PSS 0.0015 0.0035 %/% VDD = 4.5V - 5.5V, VA
= 4.5V, Code 80h
PSS 0.0015 0.0035 %/% VDD = 2.7V - 3.3V, VA
= 2.7V, Code 80h
Note 1: VAB
= V
DD , no connection on wiper.
2: Rheostat position non-linearity R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum
resistance wiper positions. R-DNL measures the relative step change from the ideal between successive tap positions. I W = 50 µA for
VDD = 3V and IW = 400 µA for VDD = 5V for 10 k version. See Figure 2-26 for test circuit.
3: INL and DNL are measured at VW with the device configured in the voltage divider or potentiometer mode. V A = V
DD and VB = 0V. DNL
specification limits of ±1 LSB max are specified monotonic operating conditions. See Figure 2-25 for test circuit.
4: Resistor terminals A,B and W have no restrictions on polarity with respect to each other. Full-scale and zero-scale error were measured
using Figure 2-25.
5: Measured at VW pin where the voltage on the adjacent V W pin is swinging full-scale.
6: Supply current is independent of current through the potentiometers.
2003 Microchip Technology Inc. DS11195C-page 5
MCP41XXX/42XXX
Absolute Maximum Ratings †
VDD...................................................................................7.0V
All inputs and outputs w.r.t. V
SS ............... -0.6V to V
DD +1.0V
Storage temperature .....................................-60°C to +150°C
Ambient temp. with power applied ................-60°C to +125°C
ESD protection on all pins .................................................. 2 kV
Notice: Stresses above those listed under “maximum rat-
ings” may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at
those or any other conditions above those indicated in the
operational listings of this specification is not implied. Expo-
sure to maximum rating conditions for extended periods may
affect device reliability.
AC TIMING CHARACTERISTICS
Electrical Characteristics: Unless otherwise indicated, V DD
= +2.7V to 5.5V, TA = -40°C to +85°C.
Parameter Sym Min. Typ. Max. Units Conditions
Clock Frequency FCLK — — 10 MHz VDD = 5V (Note 1)
Clock High Time t HI 40 — ns
Clock Low Time tLO 40 — ns
CS Fall to First Rising CLK Edge tCSSR 40 — ns
Data Input Setup Time tSU 40 — ns
Data Input Hold Time tHD 10 — ns
SCK Fall to SO Valid Propagation Delay t DO 80 ns CL = 30 pF (Note 2)
SCK Rise to CS Rise Hold Time tCHS 30 — ns
SCK Rise to CS Fall Delay tCS0 10 — ns
CS Rise to CLK Rise Hold tCS1 100 — ns
CS High Time tCSH 40 — ns
Reset Pulse Width tRS 150 ns Note 2
RS Rising to CS Falling Delay Time tRSCS 150 ns Note 2
CS rising to RS or SHDN falling delay time tSE 40 ns Note 3
CS low time tCSL 100 ns Note 3
Shutdown Pulse Width tSH 150 ns Note 3
Note 1: When using the device in the daisy-chain configuration, maximum clock frequency is determined by a combination of propagation delay
time (tDO) and data input setup time (tSU). Max. clock frequency is therefore ~ 5.8 MHz based on SCK rise and fall times of 5 ns, t HI =
40 ns, t
DO = 80 ns and tSU = 40 ns.
2: Applies only to the MCP42XXX devices.
3: Applies only when using hardware pins to exit software shutdown mode, MCP42XXX only.
MCP41XXX/42XXX
DS11195C-page 6 2003 Microchip Technology Inc.
FIGURE 1-1: Detailed Serial interface Timing.
FIGURE 1-2: Reset Timing.
FIGURE 1-3: Software Shutdown Exit Timing.
CS
SCK
SI msb in
tSU
tHD
tCSSR
tCSH
tHI tLO
tCSO
SO
tCS1
1/FCLK tCHS
tDO
(First 16 bits out are always zeros)
VOUT
±1%
±1% Error Band
tS
RS
tS
VOUT
±1%
tRS
±1% Error Band
CS
tRSCS
Code 80h is latched
on rising edge of RS
Wiper position is changed to
mid-scale (80h) if RS is held
low for 150 ns
CS
tCSL
RS
SHDN
tSH
tRS
tSE
tSE
2003 Microchip Technology Inc. DS11195C-page 7
MCP41XXX/42XXX
2.0 TYPICAL PERFORMANCE CURVES
Note: Unless otherwise indicated, curve represents 10 k, 50 k and 100 k devices, V
DD = 5V, VSS = 0V, TA = +25°C,
VB = 0V.
FIGURE 2-1: Normalized Wiper to End
Terminal Resistance vs. Code.
FIGURE 2-2: Potentiometer INL Error vs.
Code.
FIGURE 2-3: Potentiometer Mode
Tempco vs. Code.
FIGURE 2-4: Nominal Resistance 10 k
vs. Temperature.
FIGURE 2-5: Nominal Resistance 50 k
vs. Temperature.
FIGURE 2-6: Nominal Resistance 100 k
vs. Temperature.
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
0
0.2
0.4
0.6
0.8
1
0 32 64 96 128 160 192 224 256
Code (Decimal)
Normalized Resistance (
)
RWB RWA
VDD = +3V to +5V
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
0 32 64 96 128 160 192 224 256
Code (Decimal)
Potentiometer INL Error (LSB)
TA = -40°C to +85°C
Refer to Figure 2-25
-10
0
10
20
30
40
50
60
70
0 32 64 96 128 160 192 224 256
Code (Decimal)
Potentiometer Mode TempCo
(ppm / °C)
TA = -40°C to +85°C
VA = 3V
0
2
4
6
8
10
12
14
-40 -25 -10 5 20 35 50 65 80 95 110 125
Temperature (°C)
Nominal Resistance (k
)
RAB
RWB
Code = 80h
MCP41010, MCP42010 (10 k
potentiometers)
0
10
20
30
40
50
60
70
-40 -25 -10 5 20 35 50 65 80 95 110 125
Temperature (°C)
Nominal Resistance (k
)
R
AB
R
WB
Code = 80h
MCP41050, MCP42050 (50 k
potentiometers
)
0
20
40
60
80
100
120
140
-40 -25 -10 5 20 35 50 65 80 95 110 125
Temperature (°C)
Nominal Resistance (k
)
MCP41100, MCP42100 (100 k
potentiometers)
R
AB
R
WB
Code = 80h
MCP41XXX/42XXX
DS11195C-page 8 2003 Microchip Technology Inc.
Note: Unless otherwise indicated, curve represents 10 k, 50 k and 100 k devices, V
DD = 5V, VSS = 0V, TA = +25°C,
VB = 0V.
FIGURE 2-7: Rheostat INL Error vs.
Code.
FIGURE 2-8: Rheostat Mode Tempco vs.
Code.
FIGURE 2-9: Static Current vs.
Temperature.
FIGURE 2-10: Active Supply Current vs.
Temperature.
FIGURE 2-11: Active Supply Current vs.
Clock Frequency.
FIGURE 2-12: Reset & Shutdown Pins
Current vs. Voltage.
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
0 32 64 96 128 160 192 224 256
Code (Decimal)
Rheostat INL Error (LSB)
TA = +25°C
TA = +85°C
TA = -40°C
Refer to Figure 2-27
0
500
1000
1500
2000
2500
3000
0 32 64 96 128 160 192 224 256
Code (Decimal)
Rheostat Mode TempCo
(ppm / °C)
TA
= -40°C to +85°C,
VA
= no connect,
RWB measured
1
10
100
1000
-40 -25 -10 5 20 35 50 65 80 95 11
0
12
5
Temperature (°C)
Static Current (nA)
30
80
130
180
230
280
-40 -25 -10 5 20 35 50 65 80 95 110 125
Temperature (°C)
Active Supply Current (µA)
VDD = 5V
VDD = 3V
FCLK = 3 MHz
Code = FFh
0
100
200
300
400
500
600
700
800
900
1000
Clock Frequency (Hz)
Active Supply Current (mA)
A - VDD = 5.5V, Code = AAh
B - VDD = 3.3V, Code = AAh
C - VDD = 5.5V, Code = FFh
D - VDD = 3.3V, Code = FFh
A
B
C
D
1k 10k 100k 1M 10M
-7
-6
-5
-4
-3
-2
-1
0
1
0 2 4 6
RS & SHDN Pin Voltage (V)
RS & SHDN Sink Current (mA)
VDD = 5.5V
2003 Microchip Technology Inc. DS11195C-page 9
MCP41XXX/42XXX
Note: Unless otherwise indicated, curve represents 10 k, 50 k and 100 k devices, V
DD = 5V, VSS = 0V, TA = +25°C,
VB = 0V.
FIGURE 2-13: 10 k Device Wiper
Resistance Histogram.
FIGURE 2-14: 50 k, 100 k Device Wiper
Resistance Histogram.
FIGURE 2-15: One Position Settling Time.
FIGURE 2-16: Full-Scale Settling Time.
FIGURE 2-17: Digital Feed through vs.
Time.
FIGURE 2-18: Gain vs. Frequency for
10 kPotentiometer.
0
20
40
60
80
100
120
140
160
180
47 48 49 50 51 52 53 54 55 56 57 58 59
Wiper Resistance (
)
Number of Occurrences
MCP41010,MCP42010
Code = 00h,
Sample Size = 400
0
20
40
60
80
100
120
140
115 117 119 121 123 125 127 129 131 133
Wiper Resistance (
)
Number of Occurrences
MCP41050, MCP41100,
MCP42050, MCP42100
Code = 00h,
Sample Size = 796
VOUT Code = 7Fh Code = 80h
CS
CL = 17 pF
VOUT
00h
FFh
CS
CL = 27 pF
CL = 27 pF
Code = 80h
VOUT
CS
-60
-54
-48
-42
-36
-30
-24
-18
-12
-6
0
6
Frequency (Hz)
Gain (dB)
CL = 30pF, Refer to Figure 2-29
MCP41010, MCP42010 (10k potentiometers)
Code = FFh
Code = 80h
Code = 40h
Code = 20h
Code = 10h
Code = 08h
Code = 04h
Code = 02h
Code = 01h
100 1k 10k 100k 1M 10
M
2003 Microchip Technology Inc. DS11195C-page 11
MCP41XXX/42XXX
2.1 Parametric Test Circuits
FIGURE 2-25: Potentiometer Divider Non-
Linearity Error Test Circuit (DNL, INL).
FIGURE 2-26: Resistor Position Non-
Linearity Error Test Circuit (Rheostat operation
DNL, INL).
FIGURE 2-27: Wiper Resistance Test
Circuit.
FIGURE 2-28: Power Supply Sensitivity
Test Circuit (PSS, PSRR).
FIGURE 2-29: Gain vs. Frequency Test
Circuit.
FIGURE 2-30: Capacitance Test Circuit.
V+
A
BW
VMEAS*
V+ = VDD
1LSB = V+/256
DUT
*Assume infinite input impedance
+
-
A
BW
DUT
IW
*Assume infinite input impedance
VMEAS*
No Connection
+
-
B
DUT W
+
-
ISW
Rsw = 0.1V
Isw
Code = 00h
0.1V
VSS = 0 to VDD
A
V+
A
BW
DUT
VA
V+ = VDD ± 10%
PSRR (dB) = 20LOG VMEAS
)(
PSS (%/%) = VDD
VMEAS
VDD
*Assume infinite input impedance
VMEAS*
VDD
+
-
VIN
-
+
+5V
VOUT
2.5V DC
OFFSET
GND
A
B
DUT
W
~
VIN
-
+
+5V
VOUT
MCP601
2.5V DC
Offset
AB
DUT
~
MCP41XXX/42XXX
DS11195C-page 12 2003 Microchip Technology Inc.
3.0 PIN DESCRIPTIONS
3.1 PA0, PA1
Potentiometer Terminal A Connection.
3.2 PB0, PB1
Potentiometer Terminal B Connection.
3.3 PW0, PW1
Potentiometer Wiper Connection.
3.4 Chip Select (CS)
This is the SPI port chip select pin and is used to exe-
cute a new command after it has been loaded into the
shift register. This pin has a Schmitt Trigger input.
3.5 Serial Clock (SCK)
This is the SPI port clock pin and is used to clock-in
new register data. Data is clocked into the SI pin on the
rising edge of the clock and out the SO pin on the falling
edge of the clock. This pin is gated to the CS pin (i.e.,
the device will not draw any more current if the SCK pin
is toggling when the CS pin is high). This pin has a
Schmitt Trigger input.
3.6 Serial Data Input (SI)
This is the SPI port serial data input pin. The command
and data bytes are clocked into the shift register using
this pin. This pin is gated to the CS pin (i.e., the device
will not draw any more current if the SI pin is toggling
when the CS pin is high). This pin has a Schmitt Trigger
input.
3.7 Serial Data Output (SO)
(MCP42XXX devices only)
This is the SPI port serial data output pin used for
daisy-chaining more than one device. Data is clocked
out of the SO pin on the falling edge of clock. This is a
push-pull output and does not go to a high-impedance
state when CS is high. It will drive a logic-low when CS
is high.
3.8 Reset (RS)
(MCP42XXX devices only)
The Reset pin will set all potentiometers to mid-scale
(Code 80h) if this pin is brought low for at least 150 ns.
This pin should not be toggled low when the CS pin is
low. It is possible to toggle this pin when the SHDN pin
is low. In order to minimize power consumption, this pin
has an active pull-up circuit. The performance of this
circuit is shown in Figure 2-12. This pin will draw negli-
gible current at logic level ‘0’ and logic level ‘1. Do not
leave this pin floating.
3.9 Shutdown (SHDN)
(MCP42XXX devices only)
The Shutdown pin has a Schmitt Trigger input. Pulling
this pin low will put the device in a power-saving mode
where A terminal is opened and the B and W terminals
are connected for all potentiometers. This pin should
not be toggled low when the CS pin is low. In order to
minimize power consumption, this pin has an active
pull-up circuit. The performance of this circuit is shown
in Figure 2-12. This pin will draw negligible current at
logic level 0and logic level 1’. Do not leave this pin
floating.
TABLE 3-1: MCP41XXX Pins
TABLE 3-2: MCP42XXX Pins
Pin # Name Function
1 CS Chip Select
2 SCK Serial Clock
3 SI Serial Data Input
4 VSS Ground
5 PA0 Terminal A Connection For Pot 0
6 PW0 Wiper Connection For Pot 0
7 PB0 Terminal B Connection For Pot 0
8 VDD Power
Pin # Name Function
1 CS Chip Select
2 SCK Serial Clock
3 SI Serial Data Input
4 VSS Ground
5 PB1 Terminal B Connection For Pot 1
6 PW1 Wiper Connection For Pot 1
7 PA1 Terminal A Connection For Pot 1
8 PA0 Terminal A Connection For Pot 0
9 PW0 Wiper Connection For Pot 0
10 PB0 Terminal B Connection For Pot 0
11 RS Reset Input
12 SHDN Shutdown Input
13 SO Data Out for Daisy-Chaining
14 VDD Power

Produktspecifikationer

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Modell: MCP41100

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