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© 2013-2015 Microchip Technology Inc. DS60001192B-page 50-1
Section 50. CPU for Devices with MIPS32
®
microAptiv™
and M-Class Cores
This section of the manual contains the following topics:
50.1 Introduction .............................................................................................................. 50-2
50.2 Architecture Overview ............................................................................................. 50-4
50.3 PIC32 CPU Details .................................................................................................. 50-8
50.4 Special Considerations When Writing to CP0 Registers ....................................... 50-13
50.5 MIPS32 Architecture.............................................................................................. 50-14
50.6 CPU Bus................................................................................................................ 50-15
50.7 Internal System Busses......................................................................................... 50-15
50.8 Set/Clear/Invert...................................................................................................... 50-16
50.9 ALU Status Bits...................................................................................................... 50-16
50.10 Interrupt and Exception Mechanism ...................................................................... 50-17
50.11 Programming Model .............................................................................................. 50-17
50.12 Floating Point Unit (FPU)....................................................................................... 50-24
50.13 Coprocessor 0 (CP0) Registers............................................................................. 50-42
50.14 Coprocessor 1 (CP1) Registers........................................................................... 50-121
50.15 microMIPS Execution .......................................................................................... 50-132
50.16 MCU ASE Extension ........................................................................................... 50-132
50.17 MIPS DSP ASE Extension .................................................................................. 50-133
50.18 Memory Model (MCU only).................................................................................. 50-133
50.19 Memory Management (MPU only)....................................................................... 50-135
50.20 L1 Caches (MPU only) ........................................................................................ 50-141
50.21 CPU Instructions.................................................................................................. 50-145
50.22 MIPS DSP ASE Instructions ................................................................................ 50-151
50.23 CPU Initialization ................................................................................................. 50-153
50.24 Effects of a Reset ................................................................................................ 50-154
50.25 Related Application Notes ...................................................................................50-155
50.26 Revision History................................................................................................... 50-156
PIC32 Family Reference Manual
DS60001192B-page 50-2 © 2013-2015 Microchip Technology Inc.
50.1 INTRODUCTION
Depending on the device family, PIC32 devices are a complex System-on-Chip (SoC), which are
based on the microAptiv™ Microprocessor core or the M-Class Microprocessor core from
Imagination Technologies Ltd. This document provides an overview of the CPU system
architecture and features of PIC32 microcontrollers that feature these microprocessor cores.
The microAptiv Microprocessor core is a superset of the MIPS
®
M14KE™ and M14KEc™
Microprocessor cores. These cores are state of the art, 32-bit, low-power, RISC processor cores
with the enhanced MIPS32
®
Release 2 Instruction Set Architecture (ISA).
The M-Class Microprocessor core is a superset of the microAptiv™ Microprocessor core. This
32-bit, low-power, RISC processor core uses the enhanced MIPS32
®
Release 5 Instruction Set
Architecture (ISA).
Visit the Imagination Technologies Ltd. website (www.imgtec.com) to learn more about the
microprocessor cores.
Depending on the core configuration, one of two options, MCU or MPU, are used, as shown in
Table 50-1.
Table 50-1: microAptiv and M-Class Microprocessor Core Configurations
The primary difference between the MCU and MPU is the presence of an L1 cache and
TLB-based MMU on the MPU. These features are used to facilitate PIC32 designs that use
operating systems to manage virtual memory.
Note: This family reference manual section is meant to serve as a complement to device
data sheets. Depending on the device variant, this manual section may not apply to
all PIC32 devices.
Please consult the note at the beginning of the “CPU” chapter in the current device
data sheet to check whether this document supports the device you are using.
Device data sheets and family reference manual sections are available for
download from the Microchip Worldwide Web site at: http://www.microchip.com
MCU Features MPU Features
Split-bus architecture Unified bus architecture
Integrated DSP ASE (see Note 1) Integrated DSP ASE (see Note 1)
Integrated MCU™ ASE Integrated MCU ASE
microMIPS™ code compression microMIPS code compression
FMT-based MMU TLB-based MMU
Two shadow register sets Eight shadow register sets
EJTAG TAP controller EJTAG TAP controller
Performance counters Performance counters
Hardware Trace (iFlowtrace
®
) Hardware Trace (iFlowtrace)
Level One (L1) CPU cache
Note 1: This feature is not available on all devices, refer to the “CPU” chapter of the spe-
cific device data sheet to determine availability.
© 2013-2015 Microchip Technology Inc. DS60001192B-page 50-3
Section 50. CPU for Devices with MIPS32
®
microAptiv™ and M-Class Cores
50.1.1 Key Features Common to All PIC32 Devices with the microAptiv
Microprocessor Core
The following key features are common to all PIC32 devices that are based on the microAptiv
Microprocessor core:
• microMIPS variable-length instruction mode for compact code
• Vectored interrupt controller with up to 256 interrupt sources
• Atomic bit manipulations on peripheral registers (Single cycle)
• High-speed Microchip ICD port with hardware-based non-intrusive data monitoring and
application data streaming functions
• EJTAG debug port allows extensive third party debug, programming and test tools support
• Instruction controlled power management modes
• Five-stage pipelined instruction execution
• Internal code protection to help protect intellectual property
• Arithmetic saturation and overflow handling support
• Zero cycle overhead saturation and rounding operations
• Atomic read-modify-write memory-to-memory instructions
• MAC instructions with up to 4 accumulators
• Native fractional data type (Q15, Q31) with rounding support
• Digital Signal Processing (DSP) Application-Specific Extension (ASE) Revision 2, which adds
DSP capabilities with support for powerful data processing operations
• Multiply/Divide unit with a maximum issue rate of one 32 x 32 multiply per clock
50.1.2 Key Features Common to All PIC32 Devices with the M-Class
Microprocessor Core
In addition to the features described for devices with the microAptiv core, the following key
features are common to all PIC32 devices that are based on the M-Class Microprocessor core:
• Implements the latest MIPS Release 5 Architecture, which includes IP protection and
reliability for industrial controllers, Internet of Things (IoT), wearables, wireless
communications, automotive, and storage
• Floating Point Unit (FPU)
50.1.3 Related MIPS Documentation
Related MIPS documentation is available for download from the related Imagination
Technologies Ltd. product page. Please note that a login may be required to access these
documents.
Documentation for the microAptiv core is available for download at:
http://www.imgtec.com/mips/aptiv/microaptiv.asp
Documentation for the M-Class core is available for download at:
http://www.imgtec.com/mips/warrior/mclass.asp

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