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 2007-2021 Microchip Technology Inc. DS60001145AA-page 1

PIC32

1.0 DEVICE OVERVIEW

This document defines the Flash programming

specification for the PIC32 family of 32-bit

microcontrollers.

This programming specification is designed to guide

developers of external programmer tools. Customers

who are developing applications for PIC32 devices

should use development tools that already provide

support for device programming.

The major topics of discussion include:

•Section 1.0 “Device Overview”

•Section 2.0 “Programming Overview”

•Section 3.0 “Programming Steps”

•Section 4.0 “Connecting to the Device”

•Section 5.0 “EJTAG vs. ICSP”

•Section 6.0 “Pseudo Operations”

•Section 7.0 “Entering 2-Wire Enhanced ICSP

Mode”

•Section 8.0 “Check Device Status”

•Section 9.0 “Erasing the Device”

•Section 10.0 “Entering Serial Execution Mode”

•Section 11.0 “Downloading the Programming

Executive (PE)”

•Section 12.0 “Downloading a Data Block”

•Section 13.0 “Initiating a Page Erase”

•Section 14.0 “Initiating a Flash Row Write”

•Section “”

•Section 16.0 “Exiting Programming Mode”

•Section 17.0 “The Programming Executive”

•Section 18.0 “Checksum”

•Section 19.0 “Configuration Memory and Device

ID”

•Section 20.0 “TAP Controllers”

•Section 21.0 “AC/DC Characteristics and Timing

Requirements”

•Appendix A: “PIC32 Flash Memory Map”

•Appendix B: “Hex File Format”

•Appendix C: “Device IDs”

•Appendix D: “Revision History”

2.0 PROGRAMMING OVERVIEW

When in development of a programming tool, it is

necessary to understand the internal Flash program

operations of the target device and the Special

Function Registers (SFRs) used to control Flash

programming, as these same operations and registers

are used by an external programming tool and its

software. These operations and control registers are

described in the “Flash Program Memory” chapter in

the specific device data sheet, and the related “PIC32

Family Reference Manual” section. It is highly

recommended that these documents be used in

conjunction with this programming specification.

An external tool programming setup consists of an

external programmer tool and a target PIC32 device.

Figure 2-1 illustrates a typical programming setup. The

programmer tool is responsible for executing

necessary programming steps and completing the

programming operation.

FIGURE 2-1: PROGRAMMING SYSTEM

SETUP

Target PIC32 Device

CPU

On-Chip Memory

External

Programmer

PIC32 Flash Programming Specification

PIC32

DS60001145AA-page 2  2007-2021 Microchip Technology Inc.

2.1 Devices with Dual Flash Panel and

Dual Boot Regions

The PIC32MKXXXXXXD/E/F/K/L/M and PIC32MZ

families of devices incorporate several features useful

for field (self) programming of the device. These

features include dual Flash panels with dual boot

regions, an aliasing scheme for the boot regions

allowing automatic selection of boot code at start-up

and a panel swap feature for Program Flash. The two

Flash panels and their associated boot regions can be

erased and programmed separately. Refer to the

Section 48. “Memory Organization and

Permissions” (DS60001214) of the “PIC32 Family

Reference Manual” for a detailed explanation of these

features.

A development tool used for production programming

will not be concerned about most of these features with

the following exceptions:

• Ensuring the SWAP bit (NVMCON[7]) is in the

proper setting. The default setting is ‘0’ for no swap

of panels. The development tool should assume the

default setting when generating source files for the

programming tool.

• Proper handling of the aliasing of the boot memory

in the checksum calculation. The aliased sections

will be duplicates of the fixed sections. See

Section 18.0 “Checksum” for more information on

checksum calculations with aliased regions

• For PIC32MK devices, using the Erase/Retry

feature when an attempt to erase a Flash page fails

and needs to be retried. See Section 13.0

“Initiating a Page Erase” for more information.

2.2 Programming Interfaces

All PIC32 devices provide two physical interfaces to the

external programmer tool:

• 2-wire In-Circuit Serial Programming™ (ICSP™)

• 4-wire Joint Test Action Group (JTAG)

See Section 4.0 “Connecting to the Device” for

more information.

Either of these methods may use a downloadable

Programming Executive (PE). The PE executes from

the target device RAM and hides device programming

details from the programmer. It also removes overhead

associated with data transfer and improves overall data

throughput. Microchip has developed a PE that is

available for use with any external programmer, see

Section 17.0 “The Programming Executive” for

more information.

Section 3.0 “Programming Steps” describes high-

level programming steps, followed by a brief

explanation of each step. Detailed explanations are

available in corresponding sections of this document.

More information on programming commands, EJTAG,

and DC specifications are available in the following

sections:

•Section 19.0 “Configuration Memory and

Device ID”

•Section 20.0 “TAP Controllers”

•Section 21.0 “AC/DC Characteristics and

Timing Requirements”

2.3 Enhanced JTAG (EJTAG)

The 2-wire and 4-wire interfaces use the EJTAG

protocol to exchange data with the programmer. While

this document provides a working description of this

protocol as needed, advanced users are advised to

refer to the Imagination Technologies Limited web site

(www.imgtec.com) for more information.

2.4 Data Sizes

Data sizes are defined as follows:

• One word: 32 bits

• One-half word: 16 bits

• One-quarter word: 8 bits

• One Byte: 8 bits

 2007-2021 Microchip Technology Inc. DS60001145AA-page 3

PIC32

3.0 PROGRAMMING STEPS

All tool programmers must perform a common set of

steps, regardless of the actual method being used.

Figure 3-1 shows the set of steps to program PIC32

devices.

FIGURE 3-1: PROGRAMMING FLOW

The following sequence lists the programming steps

with a brief explanation of each step. More detailed

information about these steps is available in the

subsequent sections.

1. Connect to the target device.

To ensure successful programming, all required

pins must be connected to appropriate signals.

See Section 4.0 “Connecting to the Device”

for more information.

2. Place the target device in programming mode.

For 2-wire programming methods, the target

device must be placed in a special programming

mode (Enhanced ICSP™) before executing any

other steps.

See Section 7.0 “Entering 2-Wire Enhanced

ICSP Mode” for more information.

3. Check the status of the device.

Checks the status of the device to ensure it is

ready to receive information from the

programmer.

See Section 8.0 “Check Device Status” for

more information.

4. Erase the target device.

If the target memory block in the device is not

blank, or if the device is code-protected, an

erase step must be performed before

programming any new data.

See Section 9.0 “Erasing the Device” for

more information.

5. Enter programming mode.

Verifies that the device is not code-protected

and boots the TAP controller to start sending

and receiving data to and from the PIC32 CPU.

See Section 10.0 “Entering Serial Execution

Mode” for more information.

Done

Exit Programming Mode

Verify Device

Done

Initiate Flash Write

Download a Data Block

Download the PE

(Optional)

Enter Serial Exec Mode

Erase Device

Check Device Status

Start

Enter Enhanced ICSP™

(Only required for 2-wire)

Yes

Note: For the 4-wire programming methods,

Step 2 is not applicable.

PIC32

DS60001145AA-page 4  2007-2021 Microchip Technology Inc.

6. Download the Programming Executive (PE).

The PE is a small block of executable code that

is downloaded into the RAM of the target device.

It will receive and program the actual data.

See Section 11.0 “Downloading the

Programming Executive (PE)” for more

information.

7. Download the block of data to program.

All methods, with or without the PE, must

download the desired programming data into a

block of memory in RAM.

See Section 12.0 “Downloading a Data

Block” for more information.

8. Initiate Flash Write.

After downloading each block of data into RAM,

the programming sequence must be started to

program it into the target device’s Flash

memory.

See Section 14.0 “Initiating a Flash Row

Write” for more information.

9. Repeat Step 7 and Step 8 until all data blocks

are downloaded and programmed.

10. Verify the program memory.

After all programming data and Configuration

bits are programmed, the target device memory

should be read back and verified for the

matching content.

See Section “” for more information.

11. Exit the programming mode.

The newly programmed data is not effective until

either power is removed and reapplied to the

target device or an exit programming sequence

is performed.

See Section 16.0 “Exiting Programming

Mode” for more information.

Note: If the programming method being used

does not require the PE, Step 6 is not

applicable.

 2007-2021 Microchip Technology Inc. DS60001145AA-page 5

PIC32

4.0 CONNECTING TO THE DEVICE

The PIC32 family provides two possible physical

interfaces for connecting and programming the

memory contents, see Figure 4-1. For all programming

interfaces, the target device must be powered and all

required signals must be connected. In addition, the

interface must be enabled, either through its

Configuration bit, as in the case of the JTAG 4-wire

interface, or though a special initialization sequence, as

is the case for the 2-wire ICSP interface.

The JTAG interface is enabled by default in blank

devices shipped from the factory.

Enabling ICSP is described in Section 7.0 “Entering

2-Wire Enhanced ICSP Mode”.

FIGURE 4-1: PROGRAMMING

INTERFACES

4.1 4-wire Interface

One possible interface is the 4-wire JTAG (IEEE

1149.1) port. Table 4-1 lists the required pin

connections. This interface uses the following four

communication lines to transfer data to and from the

PIC32 device being programmed:

• Test Clock Input (TCK)

• Test Mode Select Input (TMS)

• Test Data Input (TDI)

• Test Data Output (TDO)

Refer to the specific device data sheet for the

connection of the signals to the device pins.

4.1.1 TEST CLOCK INPUT (TCK)

TCK is the clock that controls the updating of the TAP

controller and the shifting of data through the Instruc-

tion or selected Data registers. TCK is independent of

the processor clock with respect to both frequency and

phase.

4.1.2 TEST MODE SELECT INPUT (TMS)

TMS is the control signal for the TAP controller. This

signal is sampled on the rising edge of TCK.

4.1.3 TEST DATA INPUT (TDI)

TDI is the test data input to the Instruction or selected

Data register. This signal is sampled on the rising edge

of TCK for some TAP controller states.

4.1.4 TEST DATA OUTPUT (TDO)

TDO is the test data output from the Instruction or Data

registers. This signal changes on the falling edge of

TCK. TDO is only driven when data is shifted out,

otherwise the TDO is tri-stated.

TABLE 4-1: 4-WIRE INTERFACE PINS

Programmer

2-wire

ICSP™

4-wire

JTAG

MCLR, V

CORE

(1)

, V

DDR

(1)

PIC32

, V

(1)

Note 1: This pin is not available on all devices.

Refer to the “Pin Diagrams” or “Pin

Tables” section in the specific device data

sheet to determine availability.

Device Pin Name Pin

Type Pin Description

MCLR I Programming Enable

ENVREG(2) I Enable for On-Chip Voltage Regulator

VDD, VDDIO, VDDCORE

(2), VDDR1 8V(2), VBAT(2),

and AVDD(1) P Power Supply

VSS SS, V 1 8V(2)

, and AVSS(1) P Ground

VCAP(2) P CPU logic filter capacitor connection

TDI I Test Data In

TDO O Test Data Out

TCK I Test Clock

TMS I Test Mode State

Legend: I = Input O = Output P = Power

Note 1: All power supply and ground pins must be connected, including analog supplies (AV

DD) and ground (AVSS).

2: This pin is not available on all devices. Refer to the “Pin Diagrams” or “Pin Tables” section in the specific

device data sheet to determine availability.

PIC32

DS60001145AA-page 6  2007-2021 Microchip Technology Inc.

4.2 2-wire Interface

Another possible interface is the 2-wire ICSP port.

Table 4-2 lists the required pin connections. This

interface uses the following two communication lines to

transfer data to and from the PIC32 device being

programmed:

• Serial Program Clock (PGECx)

• Serial Program Data (PGEDx)

These signals are described in the following two

sections. Refer to the specific device data sheet for the

connection of the signals to the chip pins.

4.2.1 SERIAL PROGRAM CLOCK

(PGECX)

PGECx is the clock that controls the updating of the

TAP controller and the shifting of data through the

Instruction or selected Data registers. PGECx is

independent of the processor clock, with respect to

both frequency and phase.

4.2.2 SERIAL PROGRAM DATA (PGEDX)

PGEDx is the data input/output to the Instruction or

selected Data Registers, it is also the control signal for

the TAP controller. This signal is sampled on the falling

edge of PGECx for some TAP controller states.

TABLE 4-2: 2-WIRE INTERFACE PINS

Device

Pin Name

Programmer

Pin Name Pin Type Pin Description

MCLR MCLR P Programming Enable

ENVREG(2) N/A I Enable for On-Chip Voltage Regulator

VDD, VDDIO, VBAT(2), and AVDD(1) VDD P Power Supply

VDDCORE(2) and VDDR1 8V(2) N/A P Power Supply for DDR Interface

VSS, VSS1 8V(2), and AVSS

(1) VSS P Ground

VCAP(2) N/A P CPU Logic Filter Capacitor Connection

PGECx PGEC I Primary Programming Pin Pair: Serial Clock

PGEDx PGED I/O Primary Programming Pin Pair: Serial Data

Legend: I = Input O = Output P = Power

Note 1: All power supply and ground pins must be connected, including analog supplies (AV

DD) and ground (AVSS).

2: This pin is not available on all devices. Refer to either the “Pin Diagrams” or “Pin Tables” section in the

specific device data sheet to determine availability.

PIC32

DS60001145AA-page 10  2007-2021 Microchip Technology Inc.

5.1.3 2-WIRE TO 4-WIRE

This block converts the 2-wire ICSP interface to the

4-wire JTAG interface.

5.1.4 CPU

The CPU executes instructions at 8 MHz through the

internal oscillator.

5.1.5 FLASH CONTROLLER

The Flash controller controls erasing and programming

of the Flash memory on the device.

5.1.6 FLASH MEMORY

The PIC32 device Flash memory is divided into two

logical Flash partitions consisting of the Boot Flash

Memory (BFM) and Program Flash Memory (PFM).

The BFM begins at address 0x1FC00000, and the PFM

begins at address 0x1D000000. Each Flash partition is

divided into pages, which represent the smallest block

of memory that can be erased. Depending on the

device, page sizes are 256 words (1024 bytes), 1024

words (4096 bytes) or 4096 words (16,384 bytes). Row

size indicates the number of words that are

programmed with the row program command. There

are always 8 rows within a page; therefore, devices

with 256, 1024, and 4096 word page sizes have 32,

128, and 512 word row sizes, respectively. Table 5-1

shows the PFM, BFM, row, and page size of each

device family.

For a PIC32MZ W1 device, the BFM begins at address

0x1FC00000, and the PFM begins at address

0x10000000. The Flash is divided into pages of 1024

words or 4 kbytes, which represents the smallest block

of memory that can be erased. Row size indicates the

number of words that are programmed with row

program commands. The Flash contains 4 rows within

a page with a total row size of 256 words or 1024 bytes.

Memory locations of the BFM are reserved for the

device Configuration registers, see Section 19.0

“Configuration Memory and Device ID” for more

information.

TABLE 5-1: CODE MEMORY SIZE

PIC32 Device Row Size

(Words)

Page Size

(Words)

Boot Flash Memory Address

(Bytes) (See Note 1)

Programming Executive

(See Notes 2 and 3)

PIC32MX

110/120/130/150/170

210/220/230/350/270

(28/36/44-pin devices Only)

32 256

0x1FC00000-0x1FC00BFF (3 KB)

RIPE_11_aabbcc.hex

PIC32MX

120/130/150/170/230/250/

270/530/550/570

(64/100-pin devices Only)

PIC32MX

15X/17X/25X/27X

(28/44-pin devices Only)

0x1FC00000-0x1FC02FFF (12 KB)

PIC32MZ W1 256 1024 0x1FC00000-0x1FC0FFFF (64 KB) —

Note 1: Program Flash Memory address ranges are based on Program Flash size are as given below:

• 0x1D000000-0x1D003FFF (16 KB)

• 0x1D000000-0x1D007FFF (32 KB)

• 0x1D000000-0x1D00FFFF (64 KB)

• 0x1D000000-0x1D01FFFF (128 KB)

• 0x1D000000-0x1D03FFFF (256 KB)

• 0x1D000000-0x1D07FFFF (512 KB)

• 0x1D000000-0x1D0FFFFF (1024 KB)

• 0x1D000000-0x1D1FFFFF (2048 KB)

All Program Flash memory sizes are not supported by each family.

Program Flash Memory address ranges for PIC32MZ W1: 0x10000000-0x100FFFFF (1024 KB).

2: The Programming Executive can be obtained from the related product page on the Microchip website or it can be

located in the following MPLAB ® X IDE installation folders:

…\Microchip\MPLABX\<version>\mplab_ide\mplablibs\modules\ext\REALICE.jar

…\Microchip\MPLABX\<version>\mplab_ide\mplablibs\modules\ext\ICD3.jar

…\Microchip\MPLABX\<version>\mplab_ide\mplablibs\modules\ext\PICKIT3.jar

3: The last characters of the file name, aabbcc, vary based on the revision of the file.

PIC32

DS60001145AA-page 12  2007-2021 Microchip Technology Inc.

5.2 4-wire JTAG Details

The 4-wire interface uses standard JTAG (IEEE

1149.1-2001) interface signals.

• TCK: Test Clock – drives data in/out

• TMS: Test Mode Select – selects operational mode

• TDI: Test Data Input – data into the device

• TDO: Test Data Output – data out of the device

Since only one data line is available, the protocol is

necessarily serial (like SPI). The clock input is at the

TCK pin. Configuration is performed by manipulating a

state machine bit by bit through the TMS pin. One bit of

data is transferred in and out per TCK clock pulse at the

TDI and TDO pins. Different instruction modes can be

loaded to read the chip ID or manipulate chip functions.

Data presented to TDI must be valid for a chip-specific

setup time before, and hold time, after the rising edge

of TCK. TDO data is valid for a chip-specific time after

the falling edge of TCK, refer to Figure 5-3.

FIGURE 5-3: 4-WIRE JTAG INTERFACE

TMS

TDI

TDO

iMSb

iLSb

‘ ’1

TCK

oLSb oMSb

‘ ’1‘ ’1‘ ’1

‘ ’0‘ ’0‘ ’0

 2007-2021 Microchip Technology Inc. DS60001145AA-page 13

PIC32

5.3 2-wire ICSP Details

In ICSP mode, the 2-wire ICSP signals are time

multiplexed into the 2-wire to 4-wire block. The 2-wire

to 4-wire block then converts the signals to look like a

4-wire JTAG port to the TAP controller. The following

are two possible modes of operation:

• 4-phase ICSP

• 2-phase ICSP

5.3.1 4-PHASE ICSP

In 4-phase ICSP mode, the TDI, TDO and TMS device

pins are multiplexed onto PGEDx in four clocks, see

Figure 5-4. The Least Significant bit (LSb) is shifted

first; and TDI and TMS are sampled on the falling edge

of PGECx, while TDO is driven on the falling edge of

PGECx. The 4-phase ICSP mode is used for both read

and write data transfers.

5.3.2 2-PHASE ICSP

In 2-phase ICSP mode, the TMS and TDI device pins

are multiplexed into PGEDx in two clocks, see

Figure 5-5. The LSb is shifted first; and TDI and TMS

are sampled on the falling edge of PGECx. There is no

TDO output provided in this mode. The 2-phase ICSP

mode was designed to accelerate 2-wire, write-only

transactions.

FIGURE 5-4: 2-WIRE, 4-PHASE

Note: The packet is not actually executed until

the first clock of the next packet. To enter

2-wire, 2-phase ICSP mode, the TDOEN

bit (DDPCON[0] or CFGCON[0]) must be

set to ‘0’.

TMS

TDI

TDO

IR4

IR0

‘ ’1

TCK

‘ ’1‘ ’1‘ ’1

‘ ’0‘ ’0‘ ’0

PGECx

PGEDx pTDO = 1

TDI = IR0

TMS = 0nTDO = 0

 2007-2021 Microchip Technology Inc. DS60001145AA-page 15

PIC32

6.0 PSEUDO OPERATIONS

To simplify the description of programming details, all

operations will be described using pseudo operations.

There are several functions used in the pseudo-code

descriptions. These are used either to make the

pseudo-code more readable, to abstract

implementation-specific behavior or both. When

passing parameters with pseudo operation, the

following syntax will be used:

• 5’h0x03 – send 5-bit hexadecimal value of 3

•6’b011111 – send 6-bit binary value of 31

These functions are defined in this section, and include

the following operations:

•SetMode (mode)

•SendCommand (command)

• oData = XferData (iData)

• oData = XferFastData (iData)

• oData = XferInstruction (instruction)

6.1 SetMode Pseudo Operation

Format:

SetMode (mode)

Purpose:

To set the EJTAG state machine to a specific state.

Description:

The value of mode is clocked into the device on

signal TMS. TDI is set to a ‘0’ and TDO is ignored.

Restrictions:

None.

Example:

SetMode (6’b011111)

FIGURE 6-1: SetMode 4-WIRE

FIGURE 6-2: SetMode 2-WIRE

TMS

TDI

TDO

‘ ’1

TCK

‘ ’1‘ ’1‘ ’1‘ ’1‘ ’0

Mode = 6’b011111

PGEDx

PGECx

TDI = 0TDO = 1

TMS = 1TDI = 0TMS = 0TDO = x

Mode = 6’b011111

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